Paolo Bonzini 5b794349d3 target/i386: implement undocumented 'smsw r32' behavior ... In 32-bit mode, the higher 16 bits of the destination register are undefined. In practice CR0[31:0] is stored, just like in 64-bit mode, so just remove the "if" that currently differentiates the behavior. Backports commit c0c8445255b2b5b440c355431c8b01b7b7b7c8cf from qemu		2021-02-25 23:23:51 -05:00
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arm	target/arm: Fix temp double-free in sve ldr/str	2021-02-25 23:10:37 -05:00
i386	target/i386: implement undocumented 'smsw r32' behavior	2021-02-25 23:23:51 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00