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Richard Henderson 5ca8caf656 target/arm: Split helper_crypto_sha1_3reg 
Rather than passing an opcode to a helper, fully decode the
operation at translate time. Use clear_tail_16 to zap the
balance of the SVE register with the AdvSIMD write.

Backports commit afc8b7d32668547308bdd654a63cf5228936e0ba from qemu
2020-06-14 23:18:45 -04:00
..
arm target/arm: Split helper_crypto_sha1_3reg 2020-06-14 23:18:45 -04:00
i386 softfloat: Name compare relation enum 2020-05-21 18:08:52 -04:00
m68k target/m68k: implement opcode fetoxm1 2020-06-14 21:13:29 -04:00
mips target/mips: Support variable page size 2020-06-14 21:09:51 -04:00
riscv target/riscv: Add the lowRISC Ibex CPU 2020-06-14 22:28:55 -04:00
sparc softfloat: Name compare relation enum 2020-05-21 18:08:52 -04:00