Laurent Vivier 50aa85e560 target/m68k: implement opcode fetoxm1 ... Example provided in the launchpad bug fails with: qemu: uncaught target signal 4 (Illegal instruction) - core dumped Illegal instruction (core dumped) It appears fetoxm1 is not implemented: IN: expm1f 0x800005cc: fetoxm1x %fp2,%fp0 Disassembler disagrees with translator over instruction decoding Please report this to qemu-devel@nongnu.org (gdb) x/2hx 0x800005cc 0x800005cc: 0xf200 0x0808 This patch adds the instruction. Backports commit 250b1da35d579f42319af234f36207902ca4baa4 from qemu		2020-06-14 21:13:29 -04:00
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arm	target/arm: Allow user-mode code to write CPSR.E via MSR	2020-06-14 21:08:03 -04:00
i386	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00
m68k	target/m68k: implement opcode fetoxm1	2020-06-14 21:13:29 -04:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Add a sifive-e34 cpu type	2020-04-30 21:08:10 -04:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00