Andrew Jones 6482182ba5 target/arm: cortex-a7 and cortex-a15 have pmus ... cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise them in ID_DFR0. Let's allow them to function. This also enables the pmu cpu property to work with these cpu types, i.e. we can now do '-cpu cortex-a15,pmu=off' to remove the pmu. Backports commit a46118fc16537a593119e5b316052a98514046bb from qemu		2019-03-26 20:34:11 -04:00
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arm	target/arm: cortex-a7 and cortex-a15 have pmus	2019-03-26 20:34:11 -04:00
i386	i386: Disable OSPKE on CPU model definitions	2019-03-22 09:46:44 -04:00
m68k	target/m68k: Correct instruction emulation	2019-02-28 19:21:49 -05:00
mips	target/mips: Restore Qemu's organization of CPU definitions	2019-03-08 01:40:50 -05:00
riscv	target/riscv: Remove unused struct	2019-03-19 23:58:31 -04:00
sparc	target: Resolve repeated typedef warnings	2019-01-22 20:27:35 -05:00