Richard Henderson 64822511dd target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn ... Model gen_gvec_fn_zzz on gen_gvec_fn3 in translate-a64.c, but indicating which kind of register and in which order. Model do_zzz_fn on the other do_foo functions that take an argument set and verify sve enabled. Backports 28c4da31be6a5e501b60b77bac17652dd3211378		2021-02-26 13:53:10 -05:00
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arm	target/arm: Split out gen_gvec_fn_zzz, do_zzz_fn	2021-02-26 13:53:10 -05:00
i386	target/i386: floatx80: avoid compound literals in static initializers	2021-02-25 23:38:54 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: vector single-width integer multiply instructions	2021-02-26 10:46:26 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00