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Jim Wilson 65903cf9a4
RISC-V: Add debug support for accessing CSRs. 
Add a debugger field to CPURISCVState. Add riscv_csrrw_debug function
to set it. Disable mode checks when debugger field true.

Backports commit 753e3fe207db08ce0ef0405e8452c3397c9b9308 from qemu
2019-03-19 23:42:48 -04:00
..
arm target/arm: Check access permission to ADDVL/ADDPL/RDVL 2019-03-19 05:42:59 -04:00
i386 i386: extended the cpuid_level when Intel PT is enabled 2019-03-11 16:40:23 -04:00
m68k target/m68k: Correct instruction emulation 2019-02-28 19:21:49 -05:00
mips target/mips: Restore Qemu's organization of CPU definitions 2019-03-08 01:40:50 -05:00
riscv RISC-V: Add debug support for accessing CSRs. 2019-03-19 23:42:48 -04:00
sparc target: Resolve repeated typedef warnings 2019-01-22 20:27:35 -05:00