Michael Davidsaver 2769c6ada0 armv7m: Fix reads of CONTROL register bit 1 ... The v7m CONTROL register bit 1 is SPSEL, which indicates the stack being used. We were storing this information not in v7m.control but in the separate v7m.other_sp structure field. Unfortunately, the code handling reads of the CONTROL register didn't take account of this, and so if SPSEL was updated by an exception entry or exit then a subsequent guest read of CONTROL would get the wrong value. Using a separate structure field doesn't really gain us anything in efficiency, so drop this unnecessary complexity in favour of simply storing all the bits in v7m.control. This is a migration compatibility break for M profile CPUs only. Backports commit abc24d86cc0364f402e438fae3acb14289b40734 from qemu		2018-03-02 13:26:38 -05:00
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crypto	Drop unused crypto source files	2018-02-17 15:23:57 -05:00
exec	RAMBlocks: qemu_ram_is_shared	2018-03-02 13:05:35 -05:00
fpu	softfloat: Add float128_to_uint32_round_to_zero()	2018-03-02 08:33:09 -05:00
hw	armv7m: Fix reads of CONTROL register bit 1	2018-03-02 13:26:38 -05:00
qapi	qapi: Improve qobject visitor documentation	2018-03-02 12:24:21 -05:00
qemu	util/cutils: Change qemu_strtosz*() from int64_t to uint64_t	2018-03-02 08:58:55 -05:00
qom	tcg: add options for enabling MTTCG	2018-03-02 09:25:01 -05:00
sysemu	tcg: add options for enabling MTTCG	2018-03-02 09:25:01 -05:00
config.h	import	2015-08-21 15:04:50 +08:00
elf.h	fix merge conflicts	2017-03-10 21:04:33 +08:00
glib_compat.h	qapi: Improve qobject input visitor error reporting	2018-03-02 12:05:53 -05:00
qemu-common.h	tcg: Add EXCP_ATOMIC	2018-02-27 11:57:58 -05:00