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Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, X86)
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Richard Henderson 66e6bea084
tcg: Add INDEX_op_dupm_vec 
Allow the backend to expand dup from memory directly, instead of
forcing the value into a temp first. This is especially important
if integer/vector register moves do not exist.

Note that officially tcg_out_dupm_vec is allowed to fail.
If it did, we could fix this up relatively easily:

VECE == 32/64:
Load the value into a vector register, then dup.
Both of these must work.

VECE == 8/16:
If the value happens to be at an offset such that an aligned
load would place the desired value in the least significant
end of the register, go ahead and load w/garbage in high bits.

Load the value w/INDEX_op_ld{8,16}_i32.
Attempt a move directly to vector reg, which may fail.
Store the value into the backing store for OTS.
Load the value into the vector reg w/TCG_TYPE_I32, which must work.
Duplicate from the vector reg into itself, which must work.

All of which is well and good, except that all supported
hosts can support dupm for all vece, so all of the failure
paths would be dead code and untestable.

Backports commit 37ee55a081b7863ffab2151068dd1b2f11376914 from qemu
2019-05-16 15:38:02 -04:00
bindings support for YMM registers ymm8-ymm15 (#1079) 2019-04-16 06:35:41 -04:00
docs fix invalid script path (#975) (#976) 2019-02-28 17:02:06 -05:00
include target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
msvc msvc: Define CONFIG_TCG 2019-01-30 13:52:30 -05:00
qemu tcg: Add INDEX_op_dupm_vec 2019-05-16 15:38:02 -04:00
samples target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
tests Add missing x86_vec regression test 2019-02-28 17:08:19 -05:00
.appveyor.yml
.gitignore target/riscv: Initial introduction of the RISC-V target 2019-03-08 21:46:10 -05:00
.travis.yml use new travis osx image and brew (#935) 2018-01-05 10:29:49 +08:00
AUTHORS.TXT
Brewfile
ChangeLog
config.mk
COPYING
COPYING.LGPL2
COPYING_GLIB
CREDITS.TXT Adding Philippe Antoine to CREDITS 2018-10-06 04:50:10 -04:00
install-cmocka-linux.sh
list.c
make.sh Update help description for make.sh (#1078) 2019-04-16 06:38:53 -04:00
Makefile uc: Restore armeb target 2019-04-19 15:29:25 -04:00
msvc.bat
pkgconfig.mk
README.md add Clojure 2017-12-23 00:32:33 +08:00
uc.c uc: Restore armeb target 2019-04-19 15:29:25 -04:00
windows_export.bat

README.md

Unicorn Engine

Join the chat at https://gitter.im/unicorn-engine/chat

Build Status Build status

Unicorn is a lightweight, multi-platform, multi-architecture CPU emulator framework based on QEMU.

Unicorn offers some unparalleled features:

  • Multi-architecture: ARM, ARM64 (ARMv8), M68K, MIPS, SPARC, and X86 (16, 32, 64-bit)
  • Clean/simple/lightweight/intuitive architecture-neutral API
  • Implemented in pure C language, with bindings for Crystal, Clojure, Visual Basic, Perl, Rust, Ruby, Python, Java, .NET, Go, Delphi/Free Pascal and Haskell.
  • Native support for Windows & *nix (with Mac OSX, Linux, *BSD & Solaris confirmed)
  • High performance via Just-In-Time compilation
  • Support for fine-grained instrumentation at various levels
  • Thread-safety by design
  • Distributed under free software license GPLv2

Further information is available at http://www.unicorn-engine.org

License

This project is released under the GPL license.

Compilation & Docs

See docs/COMPILE.md file for how to compile and install Unicorn.

More documentation is available in docs/README.md.

Contact

Contact us via mailing list, email or twitter for any questions.

Contribute

If you want to contribute, please pick up something from our Github issues.

We also maintain a list of more challenged problems in a TODO list.

CREDITS.TXT records important contributors of our project.