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https://github.com/yuzu-emu/unicorn.git
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103d6f51c8
Now that MemOp has been pushed down into the memory API, and callers are encoding endianness, we can collapse byte swaps along the I/O path into the accelerator and target independent adjust_endianness. Collapsing byte swaps along the I/O path enables additional endian inversion logic, e.g. SPARC64 Invert Endian TTE bit, with redundant byte swaps cancelling out. Backports commit 9bf825bf3df4ebae3af51566c8088e3f1249a910 from qemu
706 lines
20 KiB
C
706 lines
20 KiB
C
/*
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* Physical memory access templates
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2015 Linaro, Inc.
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* Copyright (c) 2016 Red Hat, Inc.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of t ptr = MAP_RAM(mr, addr1);
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he GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* warning: addr must be aligned */
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static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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MemTxResult r;
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// Unicorn: commented out
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//bool release_lock = false;
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// Unicorn: commented out
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//RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false);
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if (l < 4 || !memory_access_is_direct(mr, false)) {
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// Unicorn: commented out
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//release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val,
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MO_32 | devend_memop(endian), attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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val = ldl_le_p(ptr);
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break;
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case DEVICE_BIG_ENDIAN:
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val = ldl_be_p(ptr);
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break;
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default:
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val = ldl_p(ptr);
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break;
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}
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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// Unicorn: If'd out
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#if 0
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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#endif
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return val;
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}
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uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldl_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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uint32_t glue(ldl_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_ldl, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t glue(ldl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_ldl_le, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t glue(ldl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_ldl_be, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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/* warning: addr must be aligned */
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static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 8;
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hwaddr addr1;
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MemTxResult r;
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// Unicorn: commented out
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//bool release_lock = false;
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// Unicorn: commented out
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//RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false);
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if (l < 8 || !memory_access_is_direct(mr, false)) {
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// Unicorn: commented out
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//release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val,
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MO_64 | devend_memop(endian), attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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val = ldq_le_p(ptr);
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break;
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case DEVICE_BIG_ENDIAN:
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val = ldq_be_p(ptr);
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break;
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default:
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val = ldq_p(ptr);
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break;
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}
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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// Unicorn: If'd out
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#if 0
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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#endif
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return val;
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}
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uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_ldq_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_ldq, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint64_t glue(ldq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_ldq_le, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_ldq_be, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 1;
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hwaddr addr1;
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MemTxResult r;
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// Unicorn: commented out
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//bool release_lock = false;
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// Unicorn: commented out
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//RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false);
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if (!memory_access_is_direct(mr, false)) {
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// Unicorn: commented out
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//release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val, MO_8, attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
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val = ldub_p(ptr);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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// Unicorn: If'd out
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#if 0
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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#endif
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return val;
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}
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uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_ldub, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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/* warning: addr must be aligned */
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static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result,
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enum device_endian endian)
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{
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uint8_t *ptr;
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uint64_t val;
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MemoryRegion *mr;
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hwaddr l = 2;
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hwaddr addr1;
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MemTxResult r;
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// Unicorn: commented out
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//bool release_lock = false;
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// Unicorn: commented out
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//RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false);
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if (l < 2 || !memory_access_is_direct(mr, false)) {
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// Unicorn: commented out
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//release_lock |= prepare_mmio_access(mr);
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/* I/O case */
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r = memory_region_dispatch_read(mr, addr1, &val,
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MO_16 | devend_memop(endian), attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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val = lduw_le_p(ptr);
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break;
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case DEVICE_BIG_ENDIAN:
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val = lduw_be_p(ptr);
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break;
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default:
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val = lduw_p(ptr);
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break;
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}
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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// Unicorn: If'd out
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#if 0
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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#endif
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return val;
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}
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uint32_t glue(address_space_lduw, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_NATIVE_ENDIAN);
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}
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uint32_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_LITTLE_ENDIAN);
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}
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uint32_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL,
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hwaddr addr, MemTxAttrs attrs, MemTxResult *result)
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{
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return glue(address_space_lduw_internal, SUFFIX)(ARG1, addr, attrs, result,
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DEVICE_BIG_ENDIAN);
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}
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uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_lduw, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
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{
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return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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/* warning: addr must be aligned. The ram page is not masked as dirty
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and the code inside is not invalidated. It is useful if the dirty
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bits are used to track modified PTEs */
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void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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MemTxResult r;
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// Unicorn: commented out
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//bool release_lock = false;
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// Unicorn: commented out
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//RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true);
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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// Unicorn: commented out
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//release_lock |= prepare_mmio_access(mr);
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r = memory_region_dispatch_write(mr, addr1, val, MO_32, attrs);
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} else {
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ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
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stl_p(ptr, val);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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// Unicorn: If'd out
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#if 0
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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#endif
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}
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void glue(stl_phys_notdirty, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
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{
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glue(address_space_stl_notdirty, SUFFIX)(ARG1, addr, val,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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/* warning: addr must be aligned */
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static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs,
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MemTxResult *result, enum device_endian endian)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 4;
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hwaddr addr1;
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MemTxResult r;
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// Unicorn: commented out
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//bool release_lock = false;
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// Unicorn: commented out
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//RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true);
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if (l < 4 || !memory_access_is_direct(mr, true)) {
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// Unicorn: commented out
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//release_lock |= prepare_mmio_access(mr);
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r = memory_region_dispatch_write(mr, addr1, val,
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MO_32 | devend_memop(endian), attrs);
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} else {
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/* RAM case */
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ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
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switch (endian) {
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case DEVICE_LITTLE_ENDIAN:
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stl_le_p(ptr, val);
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break;
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case DEVICE_BIG_ENDIAN:
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stl_be_p(ptr, val);
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break;
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default:
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stl_p(ptr, val);
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break;
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}
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INVALIDATE(mr, addr1, 4);
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r = MEMTX_OK;
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}
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if (result) {
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*result = r;
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}
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// Unicorn: If'd out
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#if 0
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if (release_lock) {
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qemu_mutex_unlock_iothread();
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}
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RCU_READ_UNLOCK();
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#endif
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}
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void glue(address_space_stl, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
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result, DEVICE_NATIVE_ENDIAN);
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}
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void glue(address_space_stl_le, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
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result, DEVICE_LITTLE_ENDIAN);
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}
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void glue(address_space_stl_be, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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glue(address_space_stl_internal, SUFFIX)(ARG1, addr, val, attrs,
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result, DEVICE_BIG_ENDIAN);
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}
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void glue(stl_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
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{
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glue(address_space_stl, SUFFIX)(ARG1, addr, val,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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void glue(stl_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
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{
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glue(address_space_stl_le, SUFFIX)(ARG1, addr, val,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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void glue(stl_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
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{
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glue(address_space_stl_be, SUFFIX)(ARG1, addr, val,
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MEMTXATTRS_UNSPECIFIED, NULL);
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}
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void glue(address_space_stb, SUFFIX)(ARG1_DECL,
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hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
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{
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uint8_t *ptr;
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MemoryRegion *mr;
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hwaddr l = 1;
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hwaddr addr1;
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MemTxResult r;
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// Unicorn: commented out
|
|
//bool release_lock = false;
|
|
|
|
// Unicorn: commented out
|
|
//RCU_READ_LOCK();
|
|
mr = TRANSLATE(addr, &addr1, &l, true);
|
|
if (!memory_access_is_direct(mr, true)) {
|
|
// Unicorn: commented out
|
|
//release_lock |= prepare_mmio_access(mr);
|
|
r = memory_region_dispatch_write(mr, addr1, val, MO_8, attrs);
|
|
} else {
|
|
/* RAM case */
|
|
ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
|
|
stb_p(ptr, val);
|
|
INVALIDATE(mr, addr1, 1);
|
|
r = MEMTX_OK;
|
|
}
|
|
if (result) {
|
|
*result = r;
|
|
}
|
|
// Unicorn: If'd out
|
|
#if 0
|
|
if (release_lock) {
|
|
qemu_mutex_unlock_iothread();
|
|
}
|
|
RCU_READ_UNLOCK();
|
|
#endif
|
|
}
|
|
|
|
void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
|
|
{
|
|
glue(address_space_stb, SUFFIX)(ARG1, addr, val,
|
|
MEMTXATTRS_UNSPECIFIED, NULL);
|
|
}
|
|
|
|
/* warning: addr must be aligned */
|
|
static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint32_t val, MemTxAttrs attrs,
|
|
MemTxResult *result, enum device_endian endian)
|
|
{
|
|
uint8_t *ptr;
|
|
MemoryRegion *mr;
|
|
hwaddr l = 2;
|
|
hwaddr addr1;
|
|
MemTxResult r;
|
|
// Unicorn: commented out
|
|
//bool release_lock = false;
|
|
|
|
// Unicorn: commented out
|
|
//RCU_READ_LOCK();
|
|
mr = TRANSLATE(addr, &addr1, &l, true);
|
|
if (l < 2 || !memory_access_is_direct(mr, true)) {
|
|
// Unicorn: commented out
|
|
//release_lock |= prepare_mmio_access(mr);
|
|
r = memory_region_dispatch_write(mr, addr1, val,
|
|
MO_16 | devend_memop(endian), attrs);
|
|
} else {
|
|
/* RAM case */
|
|
ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
|
|
switch (endian) {
|
|
case DEVICE_LITTLE_ENDIAN:
|
|
stw_le_p(ptr, val);
|
|
break;
|
|
case DEVICE_BIG_ENDIAN:
|
|
stw_be_p(ptr, val);
|
|
break;
|
|
default:
|
|
stw_p(ptr, val);
|
|
break;
|
|
}
|
|
INVALIDATE(mr, addr1, 2);
|
|
r = MEMTX_OK;
|
|
}
|
|
if (result) {
|
|
*result = r;
|
|
}
|
|
// Unicorn: If'd out
|
|
#if 0
|
|
if (release_lock) {
|
|
qemu_mutex_unlock_iothread();
|
|
}
|
|
RCU_READ_UNLOCK();
|
|
#endif
|
|
}
|
|
|
|
void glue(address_space_stw, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_NATIVE_ENDIAN);
|
|
}
|
|
|
|
void glue(address_space_stw_le, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_LITTLE_ENDIAN);
|
|
}
|
|
|
|
void glue(address_space_stw_be, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stw_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_BIG_ENDIAN);
|
|
}
|
|
|
|
void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
|
|
{
|
|
glue(address_space_stw, SUFFIX)(ARG1, addr, val,
|
|
MEMTXATTRS_UNSPECIFIED, NULL);
|
|
}
|
|
|
|
void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
|
|
{
|
|
glue(address_space_stw_le, SUFFIX)(ARG1, addr, val,
|
|
MEMTXATTRS_UNSPECIFIED, NULL);
|
|
}
|
|
|
|
void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
|
|
{
|
|
glue(address_space_stw_be, SUFFIX)(ARG1, addr, val,
|
|
MEMTXATTRS_UNSPECIFIED, NULL);
|
|
}
|
|
|
|
static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint64_t val, MemTxAttrs attrs,
|
|
MemTxResult *result, enum device_endian endian)
|
|
{
|
|
uint8_t *ptr;
|
|
MemoryRegion *mr;
|
|
hwaddr l = 8;
|
|
hwaddr addr1;
|
|
MemTxResult r;
|
|
// Unicorn: commented out
|
|
//bool release_lock = false;
|
|
|
|
// Unicorn: commented out
|
|
//RCU_READ_LOCK();
|
|
mr = TRANSLATE(addr, &addr1, &l, true);
|
|
if (l < 8 || !memory_access_is_direct(mr, true)) {
|
|
// Unicorn: commented out
|
|
//release_lock |= prepare_mmio_access(mr);
|
|
r = memory_region_dispatch_write(mr, addr1, val,
|
|
MO_64 | devend_memop(endian), attrs);
|
|
} else {
|
|
/* RAM case */
|
|
ptr = qemu_map_ram_ptr(mr->uc, mr->ram_block, addr1);
|
|
switch (endian) {
|
|
case DEVICE_LITTLE_ENDIAN:
|
|
stq_le_p(ptr, val);
|
|
break;
|
|
case DEVICE_BIG_ENDIAN:
|
|
stq_be_p(ptr, val);
|
|
break;
|
|
default:
|
|
stq_p(ptr, val);
|
|
break;
|
|
}
|
|
INVALIDATE(mr, addr1, 8);
|
|
r = MEMTX_OK;
|
|
}
|
|
if (result) {
|
|
*result = r;
|
|
}
|
|
// Unicorn: If'd out
|
|
#if 0
|
|
if (release_lock) {
|
|
qemu_mutex_unlock_iothread();
|
|
}
|
|
RCU_READ_UNLOCK();
|
|
#endif
|
|
}
|
|
|
|
void glue(address_space_stq, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_NATIVE_ENDIAN);
|
|
}
|
|
|
|
void glue(address_space_stq_le, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_LITTLE_ENDIAN);
|
|
}
|
|
|
|
void glue(address_space_stq_be, SUFFIX)(ARG1_DECL,
|
|
hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result)
|
|
{
|
|
glue(address_space_stq_internal, SUFFIX)(ARG1, addr, val, attrs, result,
|
|
DEVICE_BIG_ENDIAN);
|
|
}
|
|
|
|
void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
|
|
{
|
|
glue(address_space_stq, SUFFIX)(ARG1, addr, val,
|
|
MEMTXATTRS_UNSPECIFIED, NULL);
|
|
}
|
|
|
|
void glue(stq_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
|
|
{
|
|
glue(address_space_stq_le, SUFFIX)(ARG1, addr, val,
|
|
MEMTXATTRS_UNSPECIFIED, NULL);
|
|
}
|
|
|
|
void glue(stq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
|
|
{
|
|
glue(address_space_stq_be, SUFFIX)(ARG1, addr, val,
|
|
MEMTXATTRS_UNSPECIFIED, NULL);
|
|
}
|
|
|
|
#undef ARG1_DECL
|
|
#undef ARG1
|
|
#undef SUFFIX
|
|
#undef TRANSLATE
|
|
#undef INVALIDATE
|
|
#undef RCU_READ_LOCK
|
|
#undef RCU_READ_UNLOCK
|