unicorn/qemu/target
Peter Maydell 694058da94
target/arm: Convert double-precision register moves to decodetree
Convert the "double-precision" register moves to decodetree:
this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP.

Note that the conversion process has tightened up a few of the
UNDEF encoding checks: we now correctly forbid:
* VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10
* VMOV-from-gpr with opc1:opc2 == 0x10
* VDUP with B:E == 11
* VDUP with Q == 1 and Vn<0> == 1

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
The accesses of elements < 32 bits could be improved by doing
direct ld/st of the right size rather than 32-bit read-and-shift
or read-modify-write, but we leave this for later cleanup,
since this series is generally trying to stick to fixing
the decode.

Backports commit 9851ed9269d214c0c6feba960dd14ff09e6c34b4 from qemu
2019-06-13 17:11:56 -04:00
..
arm target/arm: Convert double-precision register moves to decodetree 2019-06-13 17:11:56 -04:00
i386 cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00
m68k cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00
mips cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00
riscv cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00
sparc cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00