unicorn/qemu/target-mips
Aurelien Jarno 88f7e01d44
target-mips: simplify LWL/LDL mask generation
The LWL/LDL instructions mask the GPR with a mask depending on the
address alignement. It is currently computed by doing:

mask = 0x7fffffffffffffffull >> (t1 ^ 63)

It's simpler to generate it by doing:

mask = ~(-1 << t1)

It uses one TCG instruction less, and it avoids a 32/64-bit constant
loading which can take a few instructions on RISC hosts.

Backports commit eb02cc3f89013612cb05df23b5441741e902bbd2 from qemu
2018-02-17 15:23:27 -05:00
..
cpu-qom.h remove slow cpu QOM casts (#815) 2017-05-02 14:56:39 +08:00
cpu.c cpu: Change cpu_exec_init() arg to cpu, not env 2018-02-17 15:23:18 -05:00
cpu.h target-mips: update mips32r5-generic into P5600 2018-02-17 15:23:27 -05:00
dsp_helper.c Added MIPS support and projects for all samples. 2017-01-23 01:05:08 +11:00
helper.c target-mips: fix offset calculation for Interrupts 2018-02-17 15:23:23 -05:00
helper.h target-mips: add ERETNC instruction and Config5.LLB bit 2018-02-13 13:33:37 -05:00
lmi_helper.c import 2015-08-21 15:04:50 +08:00
Makefile.objs import 2015-08-21 15:04:50 +08:00
mips-defs.h target-mips: fix MIPS64R6-generic configuration 2018-02-17 15:23:21 -05:00
msa_helper.c target-mips: fix to clear MSACSR.Cause 2018-02-17 15:23:22 -05:00
op_helper.c target-mips: fix offset calculation for Interrupts 2018-02-17 15:23:23 -05:00
TODO import 2015-08-21 15:04:50 +08:00
translate.c target-mips: simplify LWL/LDL mask generation 2018-02-17 15:23:27 -05:00
translate_init.c target-mips: update mips32r5-generic into P5600 2018-02-17 15:23:27 -05:00
unicorn.c Merge branch 'master' into msvc2 2017-04-21 01:17:00 +08:00
unicorn.h armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition. 2017-03-15 22:25:35 +08:00