Andrew Baumann 76cd64dd7e target/arm: implement armv8 PMUSERENR (user-mode enable bits) ... In armv8, this register implements more than a single bit, with fine-grained enables for read access to event counters, cycles counters, and write access to the software increment. This change implements those checks using custom access functions for the relevant registers. Backports commit 6ecd0b6ba0591ef280ed984103924d4bdca5ac32 from qemu		2018-03-02 12:55:46 -05:00
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arm	target/arm: implement armv8 PMUSERENR (user-mode enable bits)	2018-03-02 12:55:46 -05:00
i386	i386: Change stepping of Haswell to non-blacklisted value	2018-03-02 12:53:11 -05:00
m68k	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
mips	target-mips: Provide function to test if a CPU supports an ISA	2018-03-02 08:20:19 -05:00
sparc	cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap	2018-03-02 10:12:40 -05:00