Peter Maydell 78303d4c1b arm: Fix APSR writes via M profile MSR ... Our implementation of writes to the APSR for M-profile via the MSR instruction was badly broken. First and worst, we had the sense wrong on the test of bit 2 of the SYSm field -- this is supposed to request an APSR write if bit 2 is 0 but we were doing it if bit 2 was 1. This bug was introduced in commit 58117c9bb429cd, so hasn't been in a QEMU release. Secondly, the choice of exactly which parts of APSR should be written is defined by bits in the 'mask' field. We were not passing these through from instruction decode, making it impossible to check them in the helper. Pass the mask bits through from the instruction decode to the helper function and process them appropriately; fix the wrong sense of the SYSm bit 2 check. Invalid mask values and invalid combinations of mask and register number are UNPREDICTABLE; we choose to treat them as if the mask values were valid. Backports commit b28b3377d7e9ba35611d454d5a63ef50cab1f8c5 from qemu		2018-03-02 14:08:13 -05:00
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arm	arm: Fix APSR writes via M profile MSR	2018-03-02 14:08:13 -05:00
i386	i386: Change stepping of Haswell to non-blacklisted value	2018-03-02 12:53:11 -05:00
m68k	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
mips	target-mips: Provide function to test if a CPU supports an ISA	2018-03-02 08:20:19 -05:00
sparc	cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap	2018-03-02 10:12:40 -05:00