Peter Maydell 79feec40df target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile ... The M-profile definition of the MVFR1 ID register differs slightly from the A-profile one, and in particular the check for "does the CPU support fp16 arithmetic" is not the same. We don't currently implement any M-profile CPUs with fp16 arithmetic, so this is not yet a visible bug, but correcting the logic now disarms this beartrap for when we eventually do. Backports commit dfc523a84b06b6a4b583ed4c29d24fd980dd37a0		2021-03-01 19:17:23 -05:00
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arm	target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile	2021-03-01 19:17:23 -05:00
i386	i386/cpu: Clear FEAT_XSAVE_COMP_{LO,HI} when XSAVE is not available	2021-03-01 19:04:03 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Set instance_align on RISCVCPU TypeInfo	2021-03-01 19:00:27 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00