Peter Maydell 7aa516aff2 target/arm: Implement new v8.1M VLLDM and VLSTM encodings ... v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set). The only difference is that: * the old T1 encodings UNDEF if the implementation implements 32 Dregs (this is currently architecturally impossible for M-profile) * the new T2 encodings have the implementation-defined option to read from memory (discarding the data) or write UNKNOWN values to memory for the stack slots that would be D16-D31 We choose not to make those accesses, so for us the two instructions behave identically assuming they don't UNDEF. Backports fe6fa228a71f0eb8b8ee315452e6a7736c537b1f		2021-03-03 19:01:33 -05:00
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arm	target/arm: Implement new v8.1M VLLDM and VLSTM encodings	2021-03-03 19:01:33 -05:00
i386	x86 tcg cpus: Fix Lesser GPL version number	2021-03-02 13:33:10 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Set instance_align on RISCVCPU TypeInfo	2021-03-01 19:00:27 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00