unicorn/qemu/target
LIU Zhiwei 7d0d7338c2 target/riscv: add vector amo operations
Vector AMOs operate as if aq and rl bits were zero on each element
with regard to ordering relative to other instructions in the same hart.
Vector AMOs provide no ordering guarantee between element operations
in the same vector AMO instruction

Backports 268fcca66bde62257960ec8d859de374315a5e3d
2021-02-26 09:47:32 -05:00
..
arm target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64 2021-02-25 23:50:18 -05:00
i386 target/i386: floatx80: avoid compound literals in static initializers 2021-02-25 23:38:54 -05:00
m68k target/m68k: consolidate physical translation offset into get_physical_address() 2021-02-25 23:13:48 -05:00
mips target/mips: Support variable page size 2020-06-14 21:09:51 -04:00
riscv target/riscv: add vector amo operations 2021-02-26 09:47:32 -05:00
sparc softfloat: Name compare relation enum 2020-05-21 18:08:52 -04:00