mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-01-21 21:21:10 +00:00
320b59ddb9
clang's C11 atomic_fetch_*() functions only take a C11 atomic type
pointer argument. QEMU uses direct types (int, etc) and this causes a
compiler error when a QEMU code calls these functions in a source file
that also included <stdatomic.h> via a system header file:
$ CC=clang CXX=clang++ ./configure ... && make
../util/async.c:79:17: error: address argument to atomic operation must be a pointer to _Atomic type ('unsigned int *' invalid)
Avoid using atomic_*() names in QEMU's atomic.h since that namespace is
used by <stdatomic.h>. Prefix QEMU's APIs with 'q' so that atomic.h
and <stdatomic.h> can co-exist. I checked /usr/include on my machine and
searched GitHub for existing "qatomic_" users but there seem to be none.
This patch was generated using:
$ git grep -h -o '\<atomic\(64\)\?_[a-z0-9_]\+' include/qemu/atomic.h | \
sort -u >/tmp/changed_identifiers
$ for identifier in $(</tmp/changed_identifiers); do
sed -i "s%\<$identifier\>%q$identifier%g" \
$(git grep -I -l "\<$identifier\>")
done
I manually fixed line-wrap issues and misaligned rST tables.
Backports d73415a315471ac0b127ed3fad45c8ec5d711de1
295 lines
11 KiB
C
295 lines
11 KiB
C
/*
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* Software MMU support
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* Generate inline load/store functions for all MMU modes (typically
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* at least _user and _kernel) as well as _data versions, for all data
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* sizes.
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*
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* Used by target op helpers.
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*
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* The syntax for the accessors is:
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*
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* load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
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*
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* store: cpu_st{sign}{size}_{mmusuffix}(env, ptr, val)
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*
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* sign is:
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* (empty): for 32 and 64 bit sizes
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* mmusuffix is one of the generic suffixes "data" or "code", or
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* (for softmmu configs) a target-specific MMU mode suffix as defined
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* in target cpu.h.
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*/
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#ifndef CPU_LDST_H
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#define CPU_LDST_H
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#if defined(CONFIG_USER_ONLY)
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/* sparc32plus has 64bit long but 32bit space address
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* this can make bad result with g2h() and h2g()
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*/
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#if TARGET_VIRT_ADDR_SPACE_BITS <= 32
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typedef uint32_t abi_ptr;
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#define TARGET_ABI_FMT_ptr "%x"
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#else
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typedef uint64_t abi_ptr;
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#define TARGET_ABI_FMT_ptr "%"PRIx64
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#endif
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/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
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#define g2h(x) ((void *)((unsigned long)(abi_ptr)(x) + GUEST_BASE))
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#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
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#define h2g_valid(x) 1
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#else
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#define h2g_valid(x) ({ \
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unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
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(__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
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(!RESERVED_VA || (__guest < RESERVED_VA)); \
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})
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#endif
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#define h2g_nocheck(x) ({ \
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unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
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(abi_ptr)__ret; \
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})
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#define h2g(x) ({ \
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/* Check if given address fits target address space */ \
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assert(h2g_valid(x)); \
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h2g_nocheck(x); \
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})
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#else
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typedef target_ulong abi_ptr;
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#define TARGET_ABI_FMT_ptr TARGET_ABI_FMT_lx
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#endif
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/* The memory helpers for tcg-generated code need tcg_target_long etc. */
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#include "tcg.h"
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static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry)
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{
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#if TCG_OVERSIZED_GUEST
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return entry->addr_write;
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#else
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return qatomic_read(&entry->addr_write);
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#endif
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}
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/* Find the TLB index corresponding to the mmu_idx + address pair. */
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static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx,
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target_ulong addr)
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{
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return (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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}
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/* Find the TLB entry corresponding to the mmu_idx + address pair. */
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static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
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target_ulong addr)
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{
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return &env->tlb_table[mmu_idx][tlb_index(env, mmu_idx, addr)];
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}
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uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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int cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint64_t cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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int cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint64_t cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
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int mmu_idx, uintptr_t retaddr);
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uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_lduw_be_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsw_be_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldl_be_data(CPUArchState *env, abi_ptr ptr);
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uint64_t cpu_ldq_be_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_lduw_le_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsw_le_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldl_le_data(CPUArchState *env, abi_ptr ptr);
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uint64_t cpu_ldq_le_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint32_t cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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int cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint32_t cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint64_t cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint32_t cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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int cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint32_t cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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uint64_t cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t ra);
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void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stw_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stl_be_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stq_be_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
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void cpu_stw_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stl_le_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stq_le_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
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void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stw_be_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stl_be_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stq_be_data_ra(CPUArchState *env, abi_ptr ptr,
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uint64_t val, uintptr_t ra);
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void cpu_stw_le_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stl_le_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t ra);
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void cpu_stq_le_data_ra(CPUArchState *env, abi_ptr ptr,
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uint64_t val, uintptr_t ra);
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#ifdef TARGET_WORDS_BIGENDIAN
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# define cpu_lduw_data cpu_lduw_be_data
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# define cpu_ldsw_data cpu_ldsw_be_data
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# define cpu_ldl_data cpu_ldl_be_data
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# define cpu_ldq_data cpu_ldq_be_data
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# define cpu_lduw_data_ra cpu_lduw_be_data_ra
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# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
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# define cpu_ldl_data_ra cpu_ldl_be_data_ra
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# define cpu_ldq_data_ra cpu_ldq_be_data_ra
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# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
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# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
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# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
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# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
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# define cpu_stw_data cpu_stw_be_data
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# define cpu_stl_data cpu_stl_be_data
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# define cpu_stq_data cpu_stq_be_data
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# define cpu_stw_data_ra cpu_stw_be_data_ra
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# define cpu_stl_data_ra cpu_stl_be_data_ra
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# define cpu_stq_data_ra cpu_stq_be_data_ra
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# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
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# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
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# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
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#else
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# define cpu_lduw_data cpu_lduw_le_data
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# define cpu_ldsw_data cpu_ldsw_le_data
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# define cpu_ldl_data cpu_ldl_le_data
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# define cpu_ldq_data cpu_ldq_le_data
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# define cpu_lduw_data_ra cpu_lduw_le_data_ra
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# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
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# define cpu_ldl_data_ra cpu_ldl_le_data_ra
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# define cpu_ldq_data_ra cpu_ldq_le_data_ra
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# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
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# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
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# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
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# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
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# define cpu_stw_data cpu_stw_le_data
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# define cpu_stl_data cpu_stl_le_data
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# define cpu_stq_data cpu_stq_le_data
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# define cpu_stw_data_ra cpu_stw_le_data_ra
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# define cpu_stl_data_ra cpu_stl_le_data_ra
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# define cpu_stq_data_ra cpu_stq_le_data_ra
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# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
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# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
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# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
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#endif
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uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
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uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr);
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static inline int cpu_ldsb_code(CPUArchState *env, abi_ptr addr)
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{
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return (int8_t)cpu_ldub_code(env, addr);
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}
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static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
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{
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return (int16_t)cpu_lduw_code(env, addr);
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}
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/**
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* tlb_vaddr_to_host:
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* @env: CPUArchState
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* @addr: guest virtual address to look up
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* @access_type: 0 for read, 1 for write, 2 for execute
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* @mmu_idx: MMU index to use for lookup
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*
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* Look up the specified guest virtual index in the TCG softmmu TLB.
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* If we can translate a host virtual address suitable for direct RAM
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* access, without causing a guest exception, then return it.
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* Otherwise (TLB entry is for an I/O access, guest software
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* TLB fill required, etc) return NULL.
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*/
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#ifdef CONFIG_USER_ONLY
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static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
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MMUAccessType access_type, int mmu_idx)
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{
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return g2h(addr);
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}
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#else
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void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
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MMUAccessType access_type, int mmu_idx);
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#endif
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#endif /* CPU_LDST_H */
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