Richard Henderson 7e99995b7b target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp ... We cannot easily create "any" functions for these, because the ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero. Which means that an aarch32-only cpu will return incorrect results when testing the aarch64 registers. To use these, we must either have context or additionally test vs ARM_FEATURE_AARCH64. Backports commit 7d63183ff1a61b3f7934dc9b40b10e4fd5e100cd from qemu		2020-03-21 23:19:14 -04:00
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arm	target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp	2020-03-21 23:19:14 -04:00
i386	target/i386: check for empty register in FXAM	2020-03-21 19:43:24 -04:00
m68k	m68k: Fix regression causing Single-Step via GDB/RSP to not single step	2020-03-21 12:15:08 -04:00
mips	target/arm: fix TCG leak for fcvt half->double	2020-03-21 13:14:47 -04:00
riscv	target/riscv: update mstatus.SD when FS is set dirty	2020-03-21 12:22:56 -04:00
sparc	target/sparc: sun4u Invert Endian TTE bit	2020-01-07 19:21:30 -05:00