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unicorn/qemu/target
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Peter Maydell 808d929d7c
target/arm: Fix Cortex-R5F MVFR values 
The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.

Backports commit 3de79d335c9aa7d726865e3933d9b21781032183 from qemu
2019-06-13 16:36:48 -04:00
..
arm target/arm: Fix Cortex-R5F MVFR values 2019-06-13 16:36:48 -04:00
i386 cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00
m68k cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00
mips cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00
riscv cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00
sparc cpu: Introduce CPUNegativeOffsetState 2019-06-13 15:08:25 -04:00