Lioncash 833b0ff964 target-mips: Make CP0.Config4 and CP0.Config5 registers signed ... Make the data type used for the CP0.Config4 and CP0.Config5 registers and their mask signed, for consistency with the remaining 32-bit CP0 registers, like CP0.Config0, etc. Backports commit 8280b12c0e4b515d707509dde4ddde05d9bda4ef from qemu		2018-02-11 15:48:10 -05:00
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cpu-qom.h	remove slow cpu QOM casts (#815)	2017-05-02 14:56:39 +08:00
cpu.c	Fix for MIPS issue. (#733)	2017-01-23 12:39:34 +08:00
cpu.h	target-mips: Make CP0.Config4 and CP0.Config5 registers signed	2018-02-11 15:48:10 -05:00
dsp_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
helper.c	target-mips: Use CPU_LOG_INT for logging related to interrupts	2018-02-10 21:12:41 -05:00
helper.h	rework code/block tracing	2016-01-22 18:42:27 -08:00
lmi_helper.c	import	2015-08-21 15:04:50 +08:00
Makefile.objs	import	2015-08-21 15:04:50 +08:00
mips-defs.h	import	2015-08-21 15:04:50 +08:00
msa_helper.c	Added MIPS support and projects for all samples.	2017-01-23 01:05:08 +11:00
op_helper.c	mips: remove qemu/hw/mips/mips_int.c	2017-01-19 13:07:28 +08:00
TODO	import	2015-08-21 15:04:50 +08:00
translate.c	target-mips: Add 5KEc and 5KEf MIPS64r2 processors	2018-02-11 15:47:13 -05:00
translate_init.c	target-mips: Add 5KEc and 5KEf MIPS64r2 processors	2018-02-11 15:47:13 -05:00
unicorn.c	Merge branch 'master' into msvc2	2017-04-21 01:17:00 +08:00
unicorn.h	armeb: rename arm's and mips's *REGS_STORAGE_SIZE to avoid big-endian and little-endian's duplicated definition.	2017-03-15 22:25:35 +08:00