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https://github.com/yuzu-emu/unicorn.git
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a11dd94ce7
Cleanup in the boilerplate that each target must define. Replace sparc_env_get_cpu with env_archcpu. The combination CPU(sparc_env_get_cpu) should have used ENV_GET_CPU to begin; use env_cpu now. Backports commit 5a59fbce9141c40db0f0a5a6e17583ad9189b48b from qemu
402 lines
13 KiB
C
402 lines
13 KiB
C
/*
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* FPU op helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "fpu/softfloat.h"
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#define QT0 (env->qt0)
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#define QT1 (env->qt1)
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static target_ulong do_check_ieee_exceptions(CPUSPARCState *env, uintptr_t ra)
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{
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target_ulong status = get_float_exception_flags(&env->fp_status);
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target_ulong fsr = env->fsr;
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if (unlikely(status)) {
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/* Keep exception flags clear for next time. */
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set_float_exception_flags(0, &env->fp_status);
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/* Copy IEEE 754 flags into FSR */
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if (status & float_flag_invalid) {
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fsr |= FSR_NVC;
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}
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if (status & float_flag_overflow) {
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fsr |= FSR_OFC;
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}
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if (status & float_flag_underflow) {
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fsr |= FSR_UFC;
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}
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if (status & float_flag_divbyzero) {
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fsr |= FSR_DZC;
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}
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if (status & float_flag_inexact) {
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fsr |= FSR_NXC;
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}
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if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) {
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CPUState *cs = env_cpu(env);
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/* Unmasked exception, generate a trap. Note that while
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the helper is marked as NO_WG, we can get away with
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writing to cpu state along the exception path, since
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TCG generated code will never see the write. */
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env->fsr = fsr | FSR_FTT_IEEE_EXCP;
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cs->exception_index = TT_FP_EXCP;
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cpu_loop_exit_restore(cs, ra);
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} else {
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/* Accumulate exceptions */
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fsr |= (fsr & FSR_CEXC_MASK) << 5;
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}
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}
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return fsr;
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}
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target_ulong helper_check_ieee_exceptions(CPUSPARCState *env)
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{
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return do_check_ieee_exceptions(env, GETPC());
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}
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#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env)
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#define F_BINOP(name) \
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float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \
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float32 src2) \
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{ \
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return float32_ ## name (src1, src2, &env->fp_status); \
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} \
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float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\
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float64 src2) \
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{ \
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return float64_ ## name (src1, src2, &env->fp_status); \
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} \
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F_HELPER(name, q) \
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{ \
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QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
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}
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F_BINOP(add);
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F_BINOP(sub);
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F_BINOP(mul);
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F_BINOP(div);
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#undef F_BINOP
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float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2)
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{
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return float64_mul(float32_to_float64(src1, &env->fp_status),
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float32_to_float64(src2, &env->fp_status),
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&env->fp_status);
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}
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void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
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{
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QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
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float64_to_float128(src2, &env->fp_status),
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&env->fp_status);
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}
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float32 helper_fnegs(float32 src)
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{
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return float32_chs(src);
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}
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#ifdef TARGET_SPARC64
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float64 helper_fnegd(float64 src)
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{
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return float64_chs(src);
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}
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F_HELPER(neg, q)
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{
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QT0 = float128_chs(QT1);
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}
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#endif
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/* Integer to float conversion. */
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float32 helper_fitos(CPUSPARCState *env, int32_t src)
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{
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return int32_to_float32(src, &env->fp_status);
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}
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float64 helper_fitod(CPUSPARCState *env, int32_t src)
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{
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return int32_to_float64(src, &env->fp_status);
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}
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void helper_fitoq(CPUSPARCState *env, int32_t src)
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{
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QT0 = int32_to_float128(src, &env->fp_status);
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}
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#ifdef TARGET_SPARC64
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float32 helper_fxtos(CPUSPARCState *env, int64_t src)
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{
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return int64_to_float32(src, &env->fp_status);
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}
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float64 helper_fxtod(CPUSPARCState *env, int64_t src)
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{
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return int64_to_float64(src, &env->fp_status);
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}
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void helper_fxtoq(CPUSPARCState *env, int64_t src)
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{
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QT0 = int64_to_float128(src, &env->fp_status);
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}
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#endif
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#undef F_HELPER
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/* floating point conversion */
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float32 helper_fdtos(CPUSPARCState *env, float64 src)
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{
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return float64_to_float32(src, &env->fp_status);
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}
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float64 helper_fstod(CPUSPARCState *env, float32 src)
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{
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return float32_to_float64(src, &env->fp_status);
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}
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float32 helper_fqtos(CPUSPARCState *env)
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{
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return float128_to_float32(QT1, &env->fp_status);
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}
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void helper_fstoq(CPUSPARCState *env, float32 src)
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{
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QT0 = float32_to_float128(src, &env->fp_status);
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}
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float64 helper_fqtod(CPUSPARCState *env)
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{
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return float128_to_float64(QT1, &env->fp_status);
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}
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void helper_fdtoq(CPUSPARCState *env, float64 src)
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{
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QT0 = float64_to_float128(src, &env->fp_status);
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}
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/* Float to integer conversion. */
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int32_t helper_fstoi(CPUSPARCState *env, float32 src)
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{
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return float32_to_int32_round_to_zero(src, &env->fp_status);
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}
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int32_t helper_fdtoi(CPUSPARCState *env, float64 src)
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{
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return float64_to_int32_round_to_zero(src, &env->fp_status);
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}
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int32_t helper_fqtoi(CPUSPARCState *env)
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{
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return float128_to_int32_round_to_zero(QT1, &env->fp_status);
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}
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#ifdef TARGET_SPARC64
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int64_t helper_fstox(CPUSPARCState *env, float32 src)
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{
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return float32_to_int64_round_to_zero(src, &env->fp_status);
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}
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int64_t helper_fdtox(CPUSPARCState *env, float64 src)
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{
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return float64_to_int64_round_to_zero(src, &env->fp_status);
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}
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int64_t helper_fqtox(CPUSPARCState *env)
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{
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return float128_to_int64_round_to_zero(QT1, &env->fp_status);
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}
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#endif
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float32 helper_fabss(float32 src)
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{
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return float32_abs(src);
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}
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#ifdef TARGET_SPARC64
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float64 helper_fabsd(float64 src)
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{
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return float64_abs(src);
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}
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void helper_fabsq(CPUSPARCState *env)
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{
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QT0 = float128_abs(QT1);
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}
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#endif
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float32 helper_fsqrts(CPUSPARCState *env, float32 src)
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{
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return float32_sqrt(src, &env->fp_status);
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}
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float64 helper_fsqrtd(CPUSPARCState *env, float64 src)
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{
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return float64_sqrt(src, &env->fp_status);
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}
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void helper_fsqrtq(CPUSPARCState *env)
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{
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QT0 = float128_sqrt(QT1, &env->fp_status);
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}
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#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
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target_ulong glue(helper_, name) (CPUSPARCState *env) \
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{ \
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int ret; \
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target_ulong fsr; \
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if (E) { \
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ret = glue(size, _compare)(reg1, reg2, &env->fp_status); \
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} else { \
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ret = glue(size, _compare_quiet)(reg1, reg2, \
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&env->fp_status); \
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} \
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fsr = do_check_ieee_exceptions(env, GETPC()); \
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switch (ret) { \
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case float_relation_unordered: \
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fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
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fsr |= FSR_NVA; \
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break; \
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case float_relation_less: \
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fsr &= ~(FSR_FCC1) << FS; \
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fsr |= FSR_FCC0 << FS; \
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break; \
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case float_relation_greater: \
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fsr &= ~(FSR_FCC0) << FS; \
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fsr |= FSR_FCC1 << FS; \
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break; \
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default: \
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fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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break; \
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} \
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return fsr; \
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}
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#define GEN_FCMP_T(name, size, FS, E) \
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target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size src2)\
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{ \
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int ret; \
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target_ulong fsr; \
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if (E) { \
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ret = glue(size, _compare)(src1, src2, &env->fp_status); \
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} else { \
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ret = glue(size, _compare_quiet)(src1, src2, \
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&env->fp_status); \
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} \
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fsr = do_check_ieee_exceptions(env, GETPC()); \
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switch (ret) { \
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case float_relation_unordered: \
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fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
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break; \
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case float_relation_less: \
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fsr &= ~(FSR_FCC1 << FS); \
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fsr |= FSR_FCC0 << FS; \
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break; \
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case float_relation_greater: \
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fsr &= ~(FSR_FCC0 << FS); \
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fsr |= FSR_FCC1 << FS; \
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break; \
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default: \
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fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
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break; \
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} \
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return fsr; \
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}
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GEN_FCMP_T(fcmps, float32, 0, 0);
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GEN_FCMP_T(fcmpd, float64, 0, 0);
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GEN_FCMP_T(fcmpes, float32, 0, 1);
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GEN_FCMP_T(fcmped, float64, 0, 1);
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GEN_FCMP(fcmpq, float128, QT0, QT1, 0, 0);
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GEN_FCMP(fcmpeq, float128, QT0, QT1, 0, 1);
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#ifdef TARGET_SPARC64
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GEN_FCMP_T(fcmps_fcc1, float32, 22, 0);
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GEN_FCMP_T(fcmpd_fcc1, float64, 22, 0);
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GEN_FCMP(fcmpq_fcc1, float128, QT0, QT1, 22, 0);
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GEN_FCMP_T(fcmps_fcc2, float32, 24, 0);
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GEN_FCMP_T(fcmpd_fcc2, float64, 24, 0);
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GEN_FCMP(fcmpq_fcc2, float128, QT0, QT1, 24, 0);
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GEN_FCMP_T(fcmps_fcc3, float32, 26, 0);
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GEN_FCMP_T(fcmpd_fcc3, float64, 26, 0);
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GEN_FCMP(fcmpq_fcc3, float128, QT0, QT1, 26, 0);
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GEN_FCMP_T(fcmpes_fcc1, float32, 22, 1);
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GEN_FCMP_T(fcmped_fcc1, float64, 22, 1);
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GEN_FCMP(fcmpeq_fcc1, float128, QT0, QT1, 22, 1);
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GEN_FCMP_T(fcmpes_fcc2, float32, 24, 1);
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GEN_FCMP_T(fcmped_fcc2, float64, 24, 1);
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GEN_FCMP(fcmpeq_fcc2, float128, QT0, QT1, 24, 1);
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GEN_FCMP_T(fcmpes_fcc3, float32, 26, 1);
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GEN_FCMP_T(fcmped_fcc3, float64, 26, 1);
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GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
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#endif
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#undef GEN_FCMP_T
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#undef GEN_FCMP
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static void set_fsr(CPUSPARCState *env, target_ulong fsr)
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{
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int rnd_mode;
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switch (fsr & FSR_RD_MASK) {
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case FSR_RD_NEAREST:
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rnd_mode = float_round_nearest_even;
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break;
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default:
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case FSR_RD_ZERO:
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rnd_mode = float_round_to_zero;
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break;
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case FSR_RD_POS:
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rnd_mode = float_round_up;
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break;
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case FSR_RD_NEG:
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rnd_mode = float_round_down;
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break;
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}
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set_float_rounding_mode(rnd_mode, &env->fp_status);
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}
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target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr,
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uint32_t new_fsr)
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{
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old_fsr = (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK);
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set_fsr(env, old_fsr);
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return old_fsr;
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}
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#ifdef TARGET_SPARC64
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target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr,
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uint64_t new_fsr)
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{
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old_fsr = (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMASK);
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set_fsr(env, old_fsr);
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return old_fsr;
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}
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#endif
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