unicorn/qemu/target
LIU Zhiwei 887c29bc79 target/riscv: add vector index load and store instructions
Vector indexed operations add the contents of each element of the
vector offset operand specified by vs2 to the base effective address
to give the effective address of each element.

Backports f732560e3551c0823cee52efba993fbb8f689a36
2021-02-26 03:00:45 -05:00
..
arm target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64 2021-02-25 23:50:18 -05:00
i386 target/i386: floatx80: avoid compound literals in static initializers 2021-02-25 23:38:54 -05:00
m68k target/m68k: consolidate physical translation offset into get_physical_address() 2021-02-25 23:13:48 -05:00
mips target/mips: Support variable page size 2020-06-14 21:09:51 -04:00
riscv target/riscv: add vector index load and store instructions 2021-02-26 03:00:45 -05:00
sparc softfloat: Name compare relation enum 2020-05-21 18:08:52 -04:00