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https://github.com/yuzu-emu/unicorn.git
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bdaaac68f5
For M-profile CPUs, the architecture specifies that the NOCP exception when a coprocessor is not present or disabled should cover the entire wide range of coprocessor-space encodings, and should take precedence over UNDEF exceptions. (This is the opposite of A-profile, where checking for a disabled FPU has to happen last.) Implement this with decodetree patterns that cover the specified ranges of the encoding space. There are a few instructions (VLLDM, VLSTM, and in v8.1 also VSCCLRM) which are in copro-space but must not be NOCP'd: these must be handled also in the new m-nocp.decode so they take precedence. This is a minor behaviour change: for unallocated insn patterns in the VFP area (cp=10,11) we will now NOCP rather than UNDEF when the FPU is disabled. As well as giving us the correct architectural behaviour for v8.1M and the recommended behaviour for v8.0M, this refactoring also removes the old NOCP handling from the remains of the 'legacy decoder' in disas_thumb2_insn(), paving the way for cleaning that up. Since we don't currently have a v8.1M feature bit or any v8.1M CPUs, the minor changes to this logic that we'll need for v8.1M are marked up with TODO comments. Backports commit a3494d4671797c291c88bd414acb0aead15f7239 from qemu
89 lines
3.4 KiB
Makefile
89 lines
3.4 KiB
Makefile
obj-y += helper.o vfp_helper.o
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obj-y += cpu.o
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obj-$(TARGET_AARCH64) += cpu64.o unicorn_aarch64.o
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obj-$(TARGET_ARM) += unicorn_arm.o
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obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
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DECODETREE = $(SRC_PATH)/scripts/decodetree.py
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target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-m-nocp.inc.c: $(SRC_PATH)/target/arm/m-nocp.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --static-decode disas_m_nocp -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
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$(call quiet-command,\
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$(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\
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"GEN", $(TARGET_DIR)$@)
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target/arm/translate-sve.o: target/arm/decode-sve.inc.c
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target/arm/translate.o: target/arm/decode-m-nocp.inc.c
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target/arm/translate.o: target/arm/decode-neon-shared.inc.c
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target/arm/translate.o: target/arm/decode-neon-dp.inc.c
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target/arm/translate.o: target/arm/decode-neon-ls.inc.c
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target/arm/translate.o: target/arm/decode-vfp.inc.c
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target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
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target/arm/translate.o: target/arm/decode-a32.inc.c
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target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
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target/arm/translate.o: target/arm/decode-t32.inc.c
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target/arm/translate.o: target/arm/decode-t16.inc.c
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obj-y += tlb_helper.o debug_helper.o
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obj-y += translate.o op_helper.o
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obj-y += crypto_helper.o
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obj-y += iwmmxt_helper.o vec_helper.o neon_helper.o
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obj-y += m_helper.o
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obj-$(CONFIG_SOFTMMU) += psci.o
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obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
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obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
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obj-$(TARGET_AARCH64) += pauth_helper.o
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obj-$(TARGET_AARCH64) += mte_helper.o
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