unicorn/qemu/target
Peter Maydell 9056a93c9a
target/arm: Don't store M profile PRIMASK and FAULTMASK in daif
We currently store the M profile CPU register state PRIMASK and
FAULTMASK in the daif field of the CPU state in its I and F
bits. This is a legacy from the original implementation, which
tried to share the cpu_exec_interrupt code between A profile
and M profile. We've since separated out the two cases because
they are significantly different, so now there is no common
code between M and A profile which looks at env->daif: all the
uses are either in A-only or M-only code paths. Sharing the state
fields now is just confusing, and will make things awkward
when we implement v8M, where the PRIMASK and FAULTMASK
registers are banked between security states.

Switch M profile over to using v7m.faultmask and v7m.primask
fields for these registers.

Backports commit e6ae5981ea4b0f6feb223009a5108582e7644f8f from qemu
2018-03-04 12:56:29 -05:00
..
arm target/arm: Don't store M profile PRIMASK and FAULTMASK in daif 2018-03-04 12:56:29 -05:00
i386 target-i386/cpu: Add new EPYC CPU model 2018-03-04 12:22:27 -05:00
m68k tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00
mips target/mips: Fix RDHWR CC with icount 2018-03-04 01:35:25 -05:00
sparc tcg: Pass generic CPUState to gen_intermediate_code() 2018-03-03 23:34:18 -05:00