unicorn/qemu/include/hw/riscv/spike.h
Lioncash 94dbf9eb96
targets: Initial RISC-V port
Functionally everything is here, however it crashes for some bizarre
reason upon initialization. Yay for qemu having an overcomplicated
initialization process that's difficult to keep a mental model of.
2018-10-08 07:07:24 -04:00

17 lines
476 B
C

#ifndef HW_RISCV_H
#define HW_RISCV_H
#if defined(TARGET_RISCV32)
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
#elif defined(TARGET_RISCV64)
#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
#endif
void spike_v1_10_0_machine_init_register_types(struct uc_struct *uc);
void riscv_cpu_register_types(void *opaque);
#endif /* HW_ARM_H */