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Paolo Bonzini 96e7e32972
softmmu: support up to 12 MMU modes 
At 8k per TLB (for 64-bit host or target), 8 or more modes
make the TLBs bigger than 64k, and some RISC TCG backends do
not like that. On the affected hosts, cut the TLB size in
half---there is still a measurable speedup on PPC with the
next patch.

Backports commit 1de29aef17a7d70dbc04a7fe51e18942e3ebe313 from qemu
2018-02-13 08:34:52 -05:00
..
address-spaces.h import 2015-08-21 15:04:50 +08:00
cpu-all.h import 2015-08-21 15:04:50 +08:00
cpu-common.h delete qemu/include/exec/poison.h 2017-01-20 13:58:50 +08:00
cpu-defs.h softmmu: support up to 12 MMU modes 2018-02-13 08:34:52 -05:00
cpu_ldst.h softmmu: support up to 12 MMU modes 2018-02-13 08:34:52 -05:00
cpu_ldst_template.h This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
cputlb.h exec: make iotlb RCU-friendly 2018-02-12 15:20:39 -05:00
exec-all.h Add MemTxAttrs to the IOTLB 2018-02-12 18:38:38 -05:00
gen-icount.h tcg: Change translator-side labels to a pointer 2018-02-09 14:17:56 -05:00
helper-gen.h import 2015-08-21 15:04:50 +08:00
helper-head.h import 2015-08-21 15:04:50 +08:00
helper-proto.h import 2015-08-21 15:04:50 +08:00
helper-tcg.h This code should now build the x86_x64-softmmu part 2. 2017-01-19 22:50:28 +11:00
hwaddr.h platform.h move #3 2017-01-21 00:13:21 +11:00
ioport.h import 2015-08-21 15:04:50 +08:00
memattrs.h target-arm: Add user-mode transaction attribute 2018-02-12 20:41:58 -05:00
memory-internal.h import 2015-08-21 15:04:50 +08:00
memory.h exec.c: Add new address_space_ld*/st* functions 2018-02-12 19:22:47 -05:00
ram_addr.h we dont need to handle VGA & Migration memories 2017-01-20 17:03:39 +08:00