unicorn/qemu/target
Peter Maydell 999080382f
target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode
In ARMv7M the CPU ignores explicit writes to CONTROL.SPSEL
in Handler mode. In v8M the behaviour is slightly different:
writes to the bit are permitted but will have no effect.

We've already done the hard work to handle the value in
CONTROL.SPSEL being out of sync with what stack pointer is
actually in use, so all we need to do to fix this last loose
end is to update the condition we use to guard whether we
call write_v7m_control_spsel() on the register write.

Backports commit 83d7f86d3d27473c0aac79c1baaa5c2ab01b02d9 from qemu
2018-03-05 13:48:30 -05:00
..
arm target/arm: Allow explicit writes to CONTROL.SPSEL in Handler mode 2018-03-05 13:48:30 -05:00
i386 i386: Add EPYC-IBPB CPU model 2018-03-05 13:48:30 -05:00
m68k qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
mips qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00
sparc qom: Introduce CPUClass.tcg_initialize 2018-03-05 09:49:26 -05:00