LIU Zhiwei 9db3b70869 target/riscv: add vector configure instruction ... vsetvl and vsetvli are two configure instructions for vl, vtype. TB flags should update after configure instructions. The (ill, lmul, sew ) of vtype and the bit of (VSTART == 0 && VL == VLMAX) will be placed within tb_flags. Backports 2b7168fc43fb270fb89e1dddc17ef54714712f3a from qemu		2021-02-26 02:37:59 -05:00
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arm	target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64	2021-02-25 23:50:18 -05:00
i386	target/i386: floatx80: avoid compound literals in static initializers	2021-02-25 23:38:54 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: add vector configure instruction	2021-02-26 02:37:59 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00