Peter Maydell 9fb54a7f72 target/arm: Take exceptions on ATS instructions when needed ... The translation table walk for an ATS instruction can result in various faults. In general these are just reported back via the PAR_EL1 fault status fields, but in some cases the architecture requires that the fault is turned into an exception: * synchronous stage 2 faults of any kind during AT S1E0* and AT S1E1* instructions executed from NS EL1 fault to EL2 or EL3 * synchronous external aborts are taken as Data Abort exceptions (This is documented in the v8A Arm ARM DDI0487A.e D5.2.11 and G5.13.4.) Backports commit 0710b2fa84a4aeb925422e1e88edac49ed407c79 from qemu		2019-11-20 17:24:44 -05:00
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arm	target/arm: Take exceptions on ATS instructions when needed	2019-11-20 17:24:44 -05:00
i386	x86: Intel AVX512_BF16 feature enabling	2019-11-18 22:06:57 -05:00
m68k	target/m68k: replace LIT64 with UINT64_C macros	2019-11-18 21:05:59 -05:00
mips	target/mips: Fix emulation of ST.W in system mode	2019-11-18 23:47:33 -05:00
riscv	target/riscv: Remove redundant declaration pragmas	2019-11-18 21:22:09 -05:00
sparc	configure: Define target access alignment in configure	2019-11-18 21:41:35 -05:00