Georg Kotheimer a1edab5abf target/riscv: Add proper two-stage lookup exception detection ... The current two-stage lookup detection in riscv_cpu_do_interrupt falls short of its purpose, as all it checks is whether two-stage address translation either via the hypervisor-load store instructions or the MPRV feature would be allowed. What we really need instead is whether two-stage address translation was active when the exception was raised. However, in riscv_cpu_do_interrupt we do not have the information to reliably detect this. Therefore, when we raise a memory fault exception we have to record whether two-stage address translation is active. Backports ec352d0cab58a7bf66019057d0dfcffd9e7785a8		2021-03-30 15:21:26 -04:00
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arm	target/arm: Update sve reduction vs simd_desc	2021-03-30 14:44:53 -04:00
i386	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
m68k	target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature	2021-03-12 14:55:43 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: Add proper two-stage lookup exception detection	2021-03-30 15:21:26 -04:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00