Peter Maydell a445db5c02 target/arm: Set S and PTW in 64-bit PAR format ... In do_ats_write() we construct a PAR value based on the result of the translation. A comment says "S2WLK and FSTAGE are always zero, because we don't implement virtualization". Since we do in fact now implement virtualization, add the missing code that sets these bits based on the reported ARMMMUFaultInfo. (These bits are named PTW and S in ARMv8, so we follow that convention in the new comments in this patch.) Backports commit 0f7b791b35f24cb1333f779705a3f6472e6935de from qemu		2018-11-11 08:38:23 -05:00
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arm	target/arm: Set S and PTW in 64-bit PAR format	2018-11-11 08:38:23 -05:00
i386	i386: Add PKU on Skylake-Server CPU model	2018-11-11 08:09:47 -05:00
m68k	target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTED	2018-11-11 08:30:57 -05:00
mips	target/mips: Amend MXU ASE overview note	2018-11-11 07:30:31 -05:00
sparc	Sparc increase ttl number	2018-10-06 04:55:52 -04:00