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https://github.com/yuzu-emu/unicorn.git
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a591219ad6
The usages of this define are pure TCG and there is no architecture specific variation of the value. Localise it to the TCG engine to remove another architecture agnostic piece from cpu-defs.h. This follows on from a28177820a868eafda8fab007561cc19f41941f4 where temp_buf was moved out of the CPU_COMMON obsoleting the need for the super early definition. Backports commit 6e0b07306d1793e8402dd218d2e38a7377b5fc27 from qemu
191 lines
7.1 KiB
C
191 lines
7.1 KiB
C
/*
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* common defines for all CPUs
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_DEFS_H
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#define CPU_DEFS_H
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#ifndef NEED_CPU_H
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#error cpu.h included from common code
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#endif
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#include "config.h"
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#include "unicorn/platform.h"
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#include "qemu/osdep.h"
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#include "qemu/queue.h"
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#include "tcg-target.h"
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#ifndef CONFIG_USER_ONLY
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#include "exec/hwaddr.h"
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#endif
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#include "exec/memattrs.h"
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#ifndef TARGET_LONG_BITS
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#error TARGET_LONG_BITS must be defined before including this header
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#endif
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#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
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/* target_ulong is the type of a virtual address */
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#if TARGET_LONG_SIZE == 4
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typedef int32_t target_long;
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typedef uint32_t target_ulong;
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#define TARGET_FMT_lx "%08x"
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#define TARGET_FMT_ld "%d"
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#define TARGET_FMT_lu "%u"
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#elif TARGET_LONG_SIZE == 8
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typedef int64_t target_long;
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typedef uint64_t target_ulong;
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#define TARGET_FMT_lx "%016" PRIx64
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#define TARGET_FMT_ld "%" PRId64
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#define TARGET_FMT_lu "%" PRIu64
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#else
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#error TARGET_LONG_SIZE undefined
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#endif
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#define EXCP_INTERRUPT 0x10000 /* async interruption */
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#define EXCP_HLT 0x10001 /* hlt instruction reached */
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#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
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#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
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#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
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/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
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addresses on the same page. The top bits are the same. This allows
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TLB invalidation to quickly clear a subset of the hash table. */
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#define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2)
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#define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS)
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#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
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#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
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#if !defined(CONFIG_USER_ONLY)
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/* use a fully associative victim tlb of 8 entries */
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#define CPU_VTLB_SIZE 8
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#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32
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#define CPU_TLB_ENTRY_BITS 4
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#else
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#define CPU_TLB_ENTRY_BITS 5
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#endif
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/* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that
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* the TLB is not unnecessarily small, but still small enough for the
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* TLB lookup instruction sequence used by the TCG target.
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*
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* TCG will have to generate an operand as large as the distance between
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* env and the tlb_table[NB_MMU_MODES - 1][0].addend. For simplicity,
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* the TCG targets just round everything up to the next power of two, and
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* count bits. This works because: 1) the size of each TLB is a largish
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* power of two, 2) and because the limit of the displacement is really close
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* to a power of two, 3) the offset of tlb_table[0][0] inside env is smaller
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* than the size of a TLB.
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*
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* For example, the maximum displacement 0xFFF0 on PPC and MIPS, but TCG
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* just says "the displacement is 16 bits". TCG_TARGET_TLB_DISPLACEMENT_BITS
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* then ensures that tlb_table at least 0x8000 bytes large ("not unnecessarily
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* small": 2^15). The operand then will come up smaller than 0xFFF0 without
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* any particular care, because the TLB for a single MMU mode is larger than
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* 0x10000-0xFFF0=16 bytes. In the end, the maximum value of the operand
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* could be something like 0xC000 (the offset of the last TLB table) plus
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* 0x18 (the offset of the addend field in each TLB entry) plus the offset
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* of tlb_table inside env (which is non-trivial but not huge).
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*/
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#define CPU_TLB_BITS \
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MIN(8, \
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TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \
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(NB_MMU_MODES <= 1 ? 0 : \
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NB_MMU_MODES <= 2 ? 1 : \
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NB_MMU_MODES <= 4 ? 2 : \
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NB_MMU_MODES <= 8 ? 3 : 4))
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#define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
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typedef struct CPUTLBEntry {
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/* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
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bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
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go directly to ram.
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bit 3 : indicates that the entry is invalid
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bit 2..0 : zero
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*/
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target_ulong addr_read;
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target_ulong addr_write;
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target_ulong addr_code;
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/* Addend to virtual address to get host address. IO accesses
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use the corresponding iotlb value. */
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uintptr_t addend;
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/* padding to get a power of two size */
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#ifdef _MSC_VER
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# define TARGET_ULONG_SIZE (TARGET_LONG_BITS/8)
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# ifdef _WIN64
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# define UINTPTR_SIZE 8
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# else
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# define UINTPTR_SIZE 4
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# endif
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#define DUMMY_SIZE (1 << CPU_TLB_ENTRY_BITS) - \
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(TARGET_ULONG_SIZE * 3 + \
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((-TARGET_ULONG_SIZE * 3) & (UINTPTR_SIZE - 1)) + \
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UINTPTR_SIZE)
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#if DUMMY_SIZE > 0
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uint8_t dummy[DUMMY_SIZE];
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#endif
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#else // _MSC_VER
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uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
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(sizeof(target_ulong) * 3 +
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((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) +
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sizeof(uintptr_t))];
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#endif // _MSC_VER
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} CPUTLBEntry;
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QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
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/* The IOTLB is not accessed directly inline by generated TCG code,
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* so the CPUIOTLBEntry layout is not as critical as that of the
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* CPUTLBEntry. (This is also why we don't want to combine the two
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* structs into one.)
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*/
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typedef struct CPUIOTLBEntry {
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hwaddr addr;
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MemTxAttrs attrs;
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} CPUIOTLBEntry;
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#define CPU_COMMON_TLB \
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/* The meaning of the MMU modes is defined in the target code. */ \
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CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
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CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \
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CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
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CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \
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target_ulong tlb_flush_addr; \
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target_ulong tlb_flush_mask; \
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target_ulong vtlb_index; \
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#else
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#define CPU_COMMON_TLB
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#endif
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// Unicorn engine
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// @invalid_addr: invalid memory access address
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// @invalid_error: error code for memory access (1 = READ, 2 = WRITE)
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#define CPU_COMMON \
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/* soft mmu support */ \
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CPU_COMMON_TLB \
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uint64_t invalid_addr; \
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int invalid_error;
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#endif
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