unicorn/qemu/target
Peter Maydell a9abb7c647 target/arm: Implement M-profile "minimal RAS implementation"
For v8.1M the architecture mandates that CPUs must provide at
least the "minimal RAS implementation" from the Reliability,
Availability and Serviceability extension. This consists of:
* an ESB instruction which is a NOP
-- since it is in the HINT space we need only add a comment
* an RFSR register which will RAZ/WI
* a RAZ/WI AIRCR.IESB bit
-- the code which handles writes to AIRCR does not allow setting
of RES0 bits, so we already treat this as RAZ/WI; add a comment
noting that this is deliberate
* minimal implementation of the RAS register block at 0xe0005000
-- this will be in a subsequent commit
* setting the ID_PFR0.RAS field to 0b0010
-- we will do this when we add the Cortex-M55 CPU model

Backports 46f4976f22a4549322307b34272e053d38653243
2021-03-03 19:07:27 -05:00
..
arm target/arm: Implement M-profile "minimal RAS implementation" 2021-03-03 19:07:27 -05:00
i386 x86 tcg cpus: Fix Lesser GPL version number 2021-03-02 13:33:10 -05:00
m68k target/m68k: consolidate physical translation offset into get_physical_address() 2021-02-25 23:13:48 -05:00
mips target/mips: Support variable page size 2020-06-14 21:09:51 -04:00
riscv target/riscv: Set instance_align on RISCVCPU TypeInfo 2021-03-01 19:00:27 -05:00
sparc softfloat: Name compare relation enum 2020-05-21 18:08:52 -04:00