Daniel Müller 642a683d7a target/arm: Correctly initialize MDCR_EL2.HPMN ... When working with performance monitoring counters, we look at MDCR_EL2.HPMN as part of the check whether a counter is enabled. This check fails, because MDCR_EL2.HPMN is reset to 0, meaning that no counters are "enabled" for < EL2. That's in violation of the Arm specification, which states that > On a Warm reset, this field [MDCR_EL2.HPMN] resets to the value in > PMCR_EL0.N That's also what a comment in the code acknowledges, but the necessary adjustment seems to have been forgotten when support for more counters was added. This change fixes the issue by setting the reset value to PMCR.N, which is four. Backports d3c1183ffeb71ca3a783eae3d7e1c51e71e8a621		2021-03-04 18:34:06 -05:00
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arm	target/arm: Correctly initialize MDCR_EL2.HPMN	2021-03-04 18:34:06 -05:00
i386	target/i386: Expose VMX entry/exit load pkrs control bits	2021-03-04 18:13:36 -05:00
m68k	cpu: move cc->transaction_failed to tcg_ops	2021-03-04 17:16:41 -05:00
mips	cpu: move do_unaligned_access to tcg_ops	2021-03-04 17:20:02 -05:00
riscv	cpu: move do_unaligned_access to tcg_ops	2021-03-04 17:20:02 -05:00
sparc	cpu: move do_unaligned_access to tcg_ops	2021-03-04 17:20:02 -05:00