Philippe Mathieu-Daudé afeb8ff2dc target/arm: Restrict the Address Translate write operation to TCG accel ... Under KVM these registers are written by the hardware. Restrict the writefn handlers to TCG to avoid when building without TCG: LINK aarch64-softmmu/qemu-system-aarch64 target/arm/helper.o: In function `do_ats_write': target/arm/helper.c:3524: undefined reference to `raise_exception' Backports commit 9fb005b02dbda7f47b789b7f19bf5f73622a4756 from qemu		2020-04-30 21:31:22 -04:00
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arm	target/arm: Restrict the Address Translate write operation to TCG accel	2020-04-30 21:31:22 -04:00
i386	various: Remove suspicious '\' character outside of #define in C code	2020-04-30 07:31:45 -04:00
m68k	m68k: Fix regression causing Single-Step via GDB/RSP to not single step	2020-03-21 12:15:08 -04:00
mips	target/mips: Fix loongson multimedia condition instructions	2020-04-30 07:14:10 -04:00
riscv	target/riscv: Add a sifive-e34 cpu type	2020-04-30 21:08:10 -04:00
sparc	target/sparc: sun4u Invert Endian TTE bit	2020-01-07 19:21:30 -05:00