mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-23 22:55:32 +00:00
b2f1326437
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/boards.h"
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#include "hw/m68k/m68k.h"
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "unicorn_common.h"
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#include "uc_priv.h"
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const int M68K_REGS_STORAGE_SIZE = offsetof(CPUM68KState, tlb_table);
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static void m68k_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUM68KState *)uc->current_cpu->env_ptr)->pc = address;
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}
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void m68k_release(void* ctx);
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void m68k_release(void* ctx)
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{
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TCGContext *tcg_ctx = ctx;;
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release_common(ctx);
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g_free(tcg_ctx->tb_ctx.tbs);
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}
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void m68k_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env = uc->cpu->env_ptr;
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memset(env->aregs, 0, sizeof(env->aregs));
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memset(env->dregs, 0, sizeof(env->dregs));
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env->pc = 0;
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}
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int m68k_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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if (regid >= UC_M68K_REG_A0 && regid <= UC_M68K_REG_A7)
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*(int32_t *)value = M68K_CPU(uc, mycpu)->env.aregs[regid - UC_M68K_REG_A0];
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else if (regid >= UC_M68K_REG_D0 && regid <= UC_M68K_REG_D7)
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*(int32_t *)value = M68K_CPU(uc, mycpu)->env.dregs[regid - UC_M68K_REG_D0];
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else {
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switch(regid) {
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default: break;
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case UC_M68K_REG_PC:
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*(int32_t *)value = M68K_CPU(uc, mycpu)->env.pc;
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break;
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}
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}
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}
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return 0;
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}
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int m68k_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count)
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{
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CPUState *mycpu = uc->cpu;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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if (regid >= UC_M68K_REG_A0 && regid <= UC_M68K_REG_A7)
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M68K_CPU(uc, mycpu)->env.aregs[regid - UC_M68K_REG_A0] = *(uint32_t *)value;
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else if (regid >= UC_M68K_REG_D0 && regid <= UC_M68K_REG_D7)
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M68K_CPU(uc, mycpu)->env.dregs[regid - UC_M68K_REG_D0] = *(uint32_t *)value;
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else {
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switch(regid) {
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default: break;
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case UC_M68K_REG_PC:
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M68K_CPU(uc, mycpu)->env.pc = *(uint32_t *)value;
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc_emu_stop(uc);
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break;
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}
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}
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}
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return 0;
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}
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DEFAULT_VISIBILITY
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void m68k_uc_init(struct uc_struct* uc)
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{
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register_accel_types(uc);
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m68k_cpu_register_types(uc);
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dummy_m68k_machine_init(uc);
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uc->release = m68k_release;
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uc->reg_read = m68k_reg_read;
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uc->reg_write = m68k_reg_write;
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uc->reg_reset = m68k_reg_reset;
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uc->set_pc = m68k_set_pc;
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uc_common_init(uc);
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}
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