Peter Maydell b427549ce4 target/arm: Implement ARMv8.2-TTS2UXN ... The ARMv8.2-TTS2UXN feature extends the XN field in stage 2 translation table descriptors from just bit [54] to bits [54:53], allowing stage 2 to control execution permissions separately for EL0 and EL1. Implement the new semantics of the XN field and enable the feature for our 'max' CPU. Backports commit ce3125bed935a12e619a8253c19340ecaa899347 from qemu		2020-05-07 08:49:18 -04:00
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arm	target/arm: Implement ARMv8.2-TTS2UXN	2020-05-07 08:49:18 -04:00
i386	various: Remove suspicious '\' character outside of #define in C code	2020-04-30 07:31:45 -04:00
m68k	m68k: Fix regression causing Single-Step via GDB/RSP to not single step	2020-03-21 12:15:08 -04:00
mips	target/mips: Fix loongson multimedia condition instructions	2020-04-30 07:14:10 -04:00
riscv	target/riscv: Add a sifive-e34 cpu type	2020-04-30 21:08:10 -04:00
sparc	target/sparc: sun4u Invert Endian TTE bit	2020-01-07 19:21:30 -05:00