mirror of
https://github.com/yuzu-emu/unicorn.git
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b2f1326437
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Backports commit fcf5ef2ab52c621a4617ebbef36bf43b4003f4c0 from qemu
473 lines
11 KiB
C
473 lines
11 KiB
C
/*
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* x86 integer helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "qemu/host-utils.h"
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#include "exec/helper-proto.h"
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//#define DEBUG_MULDIV
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/* modulo 9 table */
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static const uint8_t rclb_table[32] = {
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0, 1, 2, 3, 4, 5, 6, 7,
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8, 0, 1, 2, 3, 4, 5, 6,
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7, 8, 0, 1, 2, 3, 4, 5,
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6, 7, 8, 0, 1, 2, 3, 4,
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};
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/* modulo 17 table */
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static const uint8_t rclw_table[32] = {
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0, 1, 2, 3, 4, 5, 6, 7,
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8, 9, 10, 11, 12, 13, 14, 15,
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16, 0, 1, 2, 3, 4, 5, 6,
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7, 8, 9, 10, 11, 12, 13, 14,
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};
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/* division, flags are undefined */
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void helper_divb_AL(CPUX86State *env, target_ulong t0)
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{
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unsigned int num, den, q, r;
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num = (env->regs[R_EAX] & 0xffff);
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den = (t0 & 0xff);
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if (den == 0) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q = (num / den);
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if (q > 0xff) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q &= 0xff;
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r = (num % den) & 0xff;
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
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}
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void helper_idivb_AL(CPUX86State *env, target_ulong t0)
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{
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int num, den, q, r;
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num = (int16_t)env->regs[R_EAX];
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den = (int8_t)t0;
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if (den == 0) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q = (num / den);
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if (q != (int8_t)q) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q &= 0xff;
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r = (num % den) & 0xff;
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
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}
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void helper_divw_AX(CPUX86State *env, target_ulong t0)
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{
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unsigned int num, den, q, r;
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num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
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den = (t0 & 0xffff);
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if (den == 0) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q = (num / den);
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if (q > 0xffff) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q &= 0xffff;
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r = (num % den) & 0xffff;
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
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env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
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}
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void helper_idivw_AX(CPUX86State *env, target_ulong t0)
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{
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int num, den, q, r;
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num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
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den = (int16_t)t0;
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if (den == 0) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q = (num / den);
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if (q != (int16_t)q) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q &= 0xffff;
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r = (num % den) & 0xffff;
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
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env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
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}
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void helper_divl_EAX(CPUX86State *env, target_ulong t0)
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{
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unsigned int den, r;
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uint64_t num, q;
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num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
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den = (unsigned int)t0;
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if (den == 0) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q = (num / den);
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r = (num % den);
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if (q > 0xffffffff) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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env->regs[R_EAX] = (uint32_t)q;
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env->regs[R_EDX] = (uint32_t)r;
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}
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void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
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{
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int den, r;
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int64_t num, q;
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num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
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den = (int)t0;
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if (den == 0) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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q = (num / den);
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r = (num % den);
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if (q != (int32_t)q) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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env->regs[R_EAX] = (uint32_t)q;
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env->regs[R_EDX] = (uint32_t)r;
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}
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/* bcd */
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/* XXX: exception */
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void helper_aam(CPUX86State *env, int base)
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{
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int al, ah;
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al = env->regs[R_EAX] & 0xff;
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ah = al / base;
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al = al % base;
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
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CC_DST = al;
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}
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void helper_aad(CPUX86State *env, int base)
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{
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int al, ah;
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al = env->regs[R_EAX] & 0xff;
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ah = (env->regs[R_EAX] >> 8) & 0xff;
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al = ((ah * base) + al) & 0xff;
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al;
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CC_DST = al;
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}
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void helper_aaa(CPUX86State *env)
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{
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int icarry;
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int al, ah, af;
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int eflags;
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eflags = cpu_cc_compute_all(env, CC_OP);
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af = eflags & CC_A;
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al = env->regs[R_EAX] & 0xff;
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ah = (env->regs[R_EAX] >> 8) & 0xff;
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icarry = (al > 0xf9);
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if (((al & 0x0f) > 9) || af) {
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al = (al + 6) & 0x0f;
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ah = (ah + 1 + icarry) & 0xff;
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eflags |= CC_C | CC_A;
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} else {
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eflags &= ~(CC_C | CC_A);
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al &= 0x0f;
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}
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
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CC_SRC = eflags;
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}
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void helper_aas(CPUX86State *env)
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{
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int icarry;
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int al, ah, af;
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int eflags;
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eflags = cpu_cc_compute_all(env, CC_OP);
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af = eflags & CC_A;
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al = env->regs[R_EAX] & 0xff;
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ah = (env->regs[R_EAX] >> 8) & 0xff;
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icarry = (al < 6);
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if (((al & 0x0f) > 9) || af) {
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al = (al - 6) & 0x0f;
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ah = (ah - 1 - icarry) & 0xff;
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eflags |= CC_C | CC_A;
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} else {
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eflags &= ~(CC_C | CC_A);
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al &= 0x0f;
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}
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
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CC_SRC = eflags;
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}
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void helper_daa(CPUX86State *env)
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{
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int old_al, al, af, cf;
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int eflags;
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eflags = cpu_cc_compute_all(env, CC_OP);
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cf = eflags & CC_C;
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af = eflags & CC_A;
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old_al = al = env->regs[R_EAX] & 0xff;
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eflags = 0;
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if (((al & 0x0f) > 9) || af) {
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al = (al + 6) & 0xff;
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eflags |= CC_A;
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}
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if ((old_al > 0x99) || cf) {
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al = (al + 0x60) & 0xff;
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eflags |= CC_C;
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}
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
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/* well, speed is not an issue here, so we compute the flags by hand */
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eflags |= (al == 0) << 6; /* zf */
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eflags |= parity_table[al]; /* pf */
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eflags |= (al & 0x80); /* sf */
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CC_SRC = eflags;
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}
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void helper_das(CPUX86State *env)
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{
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int al, al1, af, cf;
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int eflags;
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eflags = cpu_cc_compute_all(env, CC_OP);
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cf = eflags & CC_C;
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af = eflags & CC_A;
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al = env->regs[R_EAX] & 0xff;
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eflags = 0;
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al1 = al;
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if (((al & 0x0f) > 9) || af) {
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eflags |= CC_A;
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if (al < 6 || cf) {
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eflags |= CC_C;
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}
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al = (al - 6) & 0xff;
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}
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if ((al1 > 0x99) || cf) {
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al = (al - 0x60) & 0xff;
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eflags |= CC_C;
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}
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env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
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/* well, speed is not an issue here, so we compute the flags by hand */
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eflags |= (al == 0) << 6; /* zf */
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eflags |= parity_table[al]; /* pf */
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eflags |= (al & 0x80); /* sf */
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CC_SRC = eflags;
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}
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#ifdef TARGET_X86_64
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static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
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{
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*plow += a;
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/* carry test */
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if (*plow < a) {
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(*phigh)++;
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}
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*phigh += b;
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}
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static void neg128(uint64_t *plow, uint64_t *phigh)
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{
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*plow = ~*plow;
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*phigh = ~*phigh;
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add128(plow, phigh, 1, 0);
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}
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/* return TRUE if overflow */
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static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
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{
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uint64_t q, r, a1, a0;
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int i, qb, ab;
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a0 = *plow;
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a1 = *phigh;
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if (a1 == 0) {
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q = a0 / b;
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r = a0 % b;
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*plow = q;
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*phigh = r;
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} else {
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if (a1 >= b) {
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return 1;
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}
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/* XXX: use a better algorithm */
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for (i = 0; i < 64; i++) {
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ab = a1 >> 63;
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a1 = (a1 << 1) | (a0 >> 63);
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if (ab || a1 >= b) {
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a1 -= b;
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qb = 1;
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} else {
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qb = 0;
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}
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a0 = (a0 << 1) | qb;
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}
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#if defined(DEBUG_MULDIV)
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printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64
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": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
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*phigh, *plow, b, a0, a1);
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#endif
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*plow = a0;
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*phigh = a1;
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}
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return 0;
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}
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/* return TRUE if overflow */
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static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
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{
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int sa, sb;
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sa = ((int64_t)*phigh < 0);
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if (sa) {
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neg128(plow, phigh);
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}
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sb = (b < 0);
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if (sb) {
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b = -b;
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}
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if (div64(plow, phigh, b) != 0) {
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return 1;
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}
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if (sa ^ sb) {
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if (*plow > (1ULL << 63)) {
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return 1;
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}
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*plow = 0-*plow;
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} else {
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if (*plow >= (1ULL << 63)) {
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return 1;
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}
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}
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if (sa) {
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*phigh = 0-*phigh;
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}
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return 0;
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}
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void helper_divq_EAX(CPUX86State *env, target_ulong t0)
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{
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uint64_t r0, r1;
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if (t0 == 0) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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r0 = env->regs[R_EAX];
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r1 = env->regs[R_EDX];
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if (div64(&r0, &r1, t0)) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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env->regs[R_EAX] = r0;
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env->regs[R_EDX] = r1;
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}
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void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
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{
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uint64_t r0, r1;
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if (t0 == 0) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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r0 = env->regs[R_EAX];
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r1 = env->regs[R_EDX];
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if (idiv64(&r0, &r1, t0)) {
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raise_exception_ra(env, EXCP00_DIVZ, GETPC());
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}
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env->regs[R_EAX] = r0;
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env->regs[R_EDX] = r1;
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}
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#endif
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#if TARGET_LONG_BITS == 32
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# define ctztl ctz32
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# define clztl clz32
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#else
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# define ctztl ctz64
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# define clztl clz64
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#endif
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target_ulong helper_pdep(target_ulong src, target_ulong mask)
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{
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target_ulong dest = 0;
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int i, o;
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for (i = 0; mask != 0; i++) {
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o = ctztl(mask);
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mask &= mask - 1;
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dest |= ((src >> i) & 1) << o;
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}
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return dest;
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}
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target_ulong helper_pext(target_ulong src, target_ulong mask)
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{
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target_ulong dest = 0;
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int i, o;
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for (o = 0; mask != 0; o++) {
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i = ctztl(mask);
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mask &= mask - 1;
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dest |= ((src >> i) & 1) << o;
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}
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return dest;
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}
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#define SHIFT 0
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#include "shift_helper_template.h"
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#undef SHIFT
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#define SHIFT 1
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#include "shift_helper_template.h"
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#undef SHIFT
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#define SHIFT 2
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#include "shift_helper_template.h"
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#undef SHIFT
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#ifdef TARGET_X86_64
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#define SHIFT 3
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#include "shift_helper_template.h"
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#undef SHIFT
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#endif
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/* Test that BIT is enabled in CR4. If not, raise an illegal opcode
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exception. This reduces the requirements for rare CR4 bits being
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mapped into HFLAGS. */
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void helper_cr4_testbit(CPUX86State *env, uint32_t bit)
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{
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if (unlikely((env->cr[4] & bit) == 0)) {
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raise_exception_ra(env, EXCP06_ILLOP, GETPC());
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}
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}
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