Peter Maydell bdaaac68f5 target/arm: Do M-profile NOCP checks early and via decodetree ... For M-profile CPUs, the architecture specifies that the NOCP exception when a coprocessor is not present or disabled should cover the entire wide range of coprocessor-space encodings, and should take precedence over UNDEF exceptions. (This is the opposite of A-profile, where checking for a disabled FPU has to happen last.) Implement this with decodetree patterns that cover the specified ranges of the encoding space. There are a few instructions (VLLDM, VLSTM, and in v8.1 also VSCCLRM) which are in copro-space but must not be NOCP'd: these must be handled also in the new m-nocp.decode so they take precedence. This is a minor behaviour change: for unallocated insn patterns in the VFP area (cp=10,11) we will now NOCP rather than UNDEF when the FPU is disabled. As well as giving us the correct architectural behaviour for v8.1M and the recommended behaviour for v8.0M, this refactoring also removes the old NOCP handling from the remains of the 'legacy decoder' in disas_thumb2_insn(), paving the way for cleaning that up. Since we don't currently have a v8.1M feature bit or any v8.1M CPUs, the minor changes to this logic that we'll need for v8.1M are marked up with TODO comments. Backports commit a3494d4671797c291c88bd414acb0aead15f7239 from qemu		2021-02-26 11:17:23 -05:00
..
arm	target/arm: Do M-profile NOCP checks early and via decodetree	2021-02-26 11:17:23 -05:00
i386	target/i386: floatx80: avoid compound literals in static initializers	2021-02-25 23:38:54 -05:00
m68k	target/m68k: consolidate physical translation offset into get_physical_address()	2021-02-25 23:13:48 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: vector single-width integer multiply instructions	2021-02-26 10:46:26 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00