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unicorn/qemu/target
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Alex Bennée c590ff441c
arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 
Neither of these operations alter the floating point status registers
so we can do a pure bitwise operation, either squashing any sign
bit (ABS) or inverting it (NEG).

Backports commit 15f8a233c8c023dbc77b6fe6cd7c79eac9bee263 from qemu
2018-03-08 18:51:35 -05:00
..
arm arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 2018-03-08 18:51:35 -05:00
i386 target/*/cpu.h: remove softfloat.h 2018-03-08 09:58:47 -05:00
m68k target/*/cpu.h: remove softfloat.h 2018-03-08 09:58:47 -05:00
mips unicorn/mips: Lessen the amount of MIPS_CPU macro usage 2018-03-07 10:50:08 -05:00
sparc target/*/cpu.h: remove softfloat.h 2018-03-08 09:58:47 -05:00