Peter Maydell 0c06666800 target/arm: Implement SG instruction corner cases ... The common situation of the SG instruction is that it is executed from S&NSC memory by a CPU in NS state. That case is handled by v7m_handle_execute_nsc(). However the instruction also has defined behaviour in a couple of other cases: * SG instruction in NS memory (behaves as a NOP) * SG in S memory but CPU already secure (clears IT bits and does nothing else) * SG instruction in v8M without Security Extension (NOP) These can be implemented in translate.c. Backports commit 76eff04d166b8fe747adbe82de8b7e060e668ff9 from qemu		2018-03-05 03:47:20 -05:00
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arm	target/arm: Implement SG instruction corner cases	2018-03-05 03:47:20 -05:00
i386	tcg: remove addr argument from lookup_tb_ptr	2018-03-05 02:16:34 -05:00
m68k	target/m68k: Switch fpu_rom from make_floatx80() to make_floatx80_init()	2018-03-04 23:05:01 -05:00
mips	tcg: remove addr argument from lookup_tb_ptr	2018-03-05 02:16:34 -05:00
sparc	sparc: Fix typedef clash	2018-03-04 23:05:50 -05:00