mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-01-12 13:55:34 +00:00
cc088f84b5
Postcopy sends RAMBlock names and offsets over the wire (since it can't rely on the order of ramaddr being the same), and it starts out with HVA fault addresses from the kernel. qemu_ram_block_from_host translates a HVA into a RAMBlock, an offset in the RAMBlock and the global ram_addr_t value. Rewrite qemu_ram_addr_from_host to use qemu_ram_block_from_host. Provide qemu_ram_get_idstr since its the actual name text sent on the wire. Backports commit 422148d3e56c3c9a07c0cf36c1e0a0b76f09c357 from qemu
126 lines
4.5 KiB
C
126 lines
4.5 KiB
C
#ifndef CPU_COMMON_H
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#define CPU_COMMON_H 1
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/* CPU interfaces that are target independent. */
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struct uc_struct;
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#ifndef CONFIG_USER_ONLY
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#include "exec/hwaddr.h"
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#endif
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#include "qemu/bswap.h"
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#include "qemu/queue.h"
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#include "qemu/fprintf-fn.h"
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#include "qemu/typedefs.h"
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typedef enum MMUAccessType {
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MMU_DATA_LOAD = 0,
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MMU_DATA_STORE = 1,
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MMU_INST_FETCH = 2
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} MMUAccessType;
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#if !defined(CONFIG_USER_ONLY)
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enum device_endian {
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DEVICE_NATIVE_ENDIAN,
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DEVICE_BIG_ENDIAN,
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DEVICE_LITTLE_ENDIAN,
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};
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/* address in the RAM (different from a physical address) */
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#if defined(CONFIG_XEN_BACKEND)
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typedef uint64_t ram_addr_t;
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# define RAM_ADDR_MAX UINT64_MAX
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# define RAM_ADDR_FMT "%" PRIx64
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#else
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typedef uintptr_t ram_addr_t;
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# define RAM_ADDR_MAX UINTPTR_MAX
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# define RAM_ADDR_FMT "%" PRIxPTR
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#endif
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extern ram_addr_t ram_size;
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/* memory API */
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typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
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typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
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void qemu_ram_remap(struct uc_struct *uc, ram_addr_t addr, ram_addr_t length);
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/* This should not be used by devices. */
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MemoryRegion *qemu_ram_addr_from_host(struct uc_struct* uc, void *ptr, ram_addr_t *ram_addr);
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RAMBlock *qemu_ram_block_from_host(struct uc_struct* uc, void *ptr, bool round_offset,
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ram_addr_t *ram_addr, ram_addr_t *offset);
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void qemu_ram_set_idstr(struct uc_struct *uc, ram_addr_t addr, const char *name, DeviceState *dev);
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void qemu_ram_unset_idstr(struct uc_struct *uc, ram_addr_t addr);
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const char *qemu_ram_get_idstr(RAMBlock *rb);
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bool cpu_physical_memory_rw(AddressSpace *as, hwaddr addr, uint8_t *buf,
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int len, int is_write);
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static inline void cpu_physical_memory_read(AddressSpace *as, hwaddr addr,
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void *buf, int len)
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{
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cpu_physical_memory_rw(as, addr, buf, len, 0);
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}
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static inline void cpu_physical_memory_write(AddressSpace *as, hwaddr addr,
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const void *buf, int len)
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{
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cpu_physical_memory_rw(as, addr, (void *)buf, len, 1);
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}
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void *cpu_physical_memory_map(AddressSpace *as, hwaddr addr,
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hwaddr *plen,
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int is_write);
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void cpu_physical_memory_unmap(AddressSpace *as, void *buffer, hwaddr len,
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int is_write, hwaddr access_len);
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void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
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bool cpu_physical_memory_is_io(AddressSpace *as, hwaddr phys_addr);
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/* Coalesced MMIO regions are areas where write operations can be reordered.
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* This usually implies that write operations are side-effect free. This allows
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* batching which can make a major impact on performance when using
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* virtualization.
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*/
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void qemu_flush_coalesced_mmio_buffer(void);
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uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
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uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr);
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uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr);
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uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
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uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
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uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
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uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
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void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
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void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
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#ifdef NEED_CPU_H
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uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
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uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
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uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
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void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
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void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
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void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
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#endif
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void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
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const uint8_t *buf, int len);
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void cpu_flush_icache_range(AddressSpace *as, hwaddr start, int len);
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extern struct MemoryRegion io_mem_rom;
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extern struct MemoryRegion io_mem_notdirty;
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typedef void (RAMBlockIterFunc)(void *host_addr,
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ram_addr_t offset, ram_addr_t length, void *opaque);
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void qemu_ram_foreach_block(struct uc_struct *uc, RAMBlockIterFunc func, void *opaque);
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#endif
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#endif /* !CPU_COMMON_H */
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