mirror of
https://github.com/yuzu-emu/unicorn.git
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5f6e7bbdbd
The number of actual invocations of ctpop itself does not warrent an opcode, but it is very helpful for POWER7 to use in generating an expansion for ctz. Backports commit a768e4e99247911f00c5c0267c12d4e207d5f6cc from qemu
145 lines
4.8 KiB
C
145 lines
4.8 KiB
C
/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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* Copyright (c) 2008 Andrzej Zaborowski
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef ARM_TCG_TARGET_H
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#define ARM_TCG_TARGET_H
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/* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */
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#ifndef __ARM_ARCH
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# if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \
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|| defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \
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|| defined(__ARM_ARCH_7EM__)
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# define __ARM_ARCH 7
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# elif defined(__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \
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|| defined(__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \
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|| defined(__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__)
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# define __ARM_ARCH 6
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# elif defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5E__) \
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|| defined(__ARM_ARCH_5T__) || defined(__ARM_ARCH_5TE__) \
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|| defined(__ARM_ARCH_5TEJ__)
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# define __ARM_ARCH 5
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# else
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# define __ARM_ARCH 4
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# endif
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#endif
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extern int arm_arch;
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#if defined(__ARM_ARCH_5T__) \
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|| defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5TEJ__)
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# define use_armv5t_instructions 1
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#else
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# define use_armv5t_instructions use_armv6_instructions
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#endif
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#define use_armv6_instructions (__ARM_ARCH >= 6 || arm_arch >= 6)
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#define use_armv7_instructions (__ARM_ARCH >= 7 || arm_arch >= 7)
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#undef TCG_TARGET_STACK_GROWSUP
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#define TCG_TARGET_INSN_UNIT_SIZE 4
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#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
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typedef enum {
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TCG_REG_R0 = 0,
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TCG_REG_R1,
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TCG_REG_R2,
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TCG_REG_R3,
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TCG_REG_R4,
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TCG_REG_R5,
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TCG_REG_R6,
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TCG_REG_R7,
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TCG_REG_R8,
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TCG_REG_R9,
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TCG_REG_R10,
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TCG_REG_R11,
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TCG_REG_R12,
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TCG_REG_R13,
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TCG_REG_R14,
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TCG_REG_PC,
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} TCGReg;
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#define TCG_TARGET_NB_REGS 16
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#ifdef __ARM_ARCH_EXT_IDIV__
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#define use_idiv_instructions 1
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#else
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extern bool use_idiv_instructions_rt;
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#define use_idiv_instructions use_idiv_instructions_rt
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#endif
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_R13
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#define TCG_TARGET_STACK_ALIGN 8
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#define TCG_TARGET_CALL_ALIGN_ARGS 1
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#define TCG_TARGET_CALL_STACK_OFFSET 0
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/* optional instructions */
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#define TCG_TARGET_HAS_ext8s_i32 1
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#define TCG_TARGET_HAS_ext16s_i32 1
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#define TCG_TARGET_HAS_ext8u_i32 0 /* and r0, r1, #0xff */
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#define TCG_TARGET_HAS_ext16u_i32 1
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#define TCG_TARGET_HAS_bswap16_i32 1
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#define TCG_TARGET_HAS_bswap32_i32 1
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#define TCG_TARGET_HAS_not_i32 1
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#define TCG_TARGET_HAS_neg_i32 1
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#define TCG_TARGET_HAS_rot_i32 1
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#define TCG_TARGET_HAS_andc_i32 1
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#define TCG_TARGET_HAS_orc_i32 0
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#define TCG_TARGET_HAS_eqv_i32 0
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#define TCG_TARGET_HAS_nand_i32 0
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_clz_i32 use_armv5t_instructions
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#define TCG_TARGET_HAS_ctz_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_ctpop_i32 0
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#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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#define TCG_TARGET_HAS_muls2_i32 1
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#define TCG_TARGET_HAS_muluh_i32 0
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#define TCG_TARGET_HAS_mulsh_i32 0
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#define TCG_TARGET_HAS_div_i32 use_idiv_instructions
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#define TCG_TARGET_HAS_rem_i32 0
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enum {
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TCG_AREG0 = TCG_REG_R6,
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};
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static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
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{
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#if QEMU_GNUC_PREREQ(4, 1)
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__builtin___clear_cache((char *) start, (char *) stop);
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#else
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register uintptr_t _beg __asm("a1") = start;
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register uintptr_t _end __asm("a2") = stop;
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register uintptr_t _flg __asm("a3") = 0;
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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#endif
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}
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#endif
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