Georg Kotheimer d18b402732 target/riscv: Fix read and write accesses to vsip and vsie ... The previous implementation was broken in many ways: - Used mideleg instead of hideleg to mask accesses - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...) Backports 9d5451e077cd84809bcdf460c39b5f4fec17fc79		2021-03-30 15:16:10 -04:00
..
arm	target/arm: Update sve reduction vs simd_desc	2021-03-30 14:44:53 -04:00
i386	qemu/atomic.h: rename atomic_ to qatomic_	2021-03-08 14:34:35 -05:00
m68k	target/m68k: add M68K_FEATURE_UNALIGNED_DATA feature	2021-03-12 14:55:43 -05:00
mips	mips: Fix build	2021-03-05 08:51:51 -05:00
riscv	target/riscv: Fix read and write accesses to vsip and vsie	2021-03-30 15:16:10 -04:00
sparc	sparc: Fix build	2021-03-05 08:54:43 -05:00