Peter Maydell d25998ba7d target/arm: Convert Neon 3-reg-diff prewidening ops to decodetree ... Convert the "pre-widening" insns VADDL, VSUBL, VADDW and VSUBW in the Neon 3-registers-different-lengths group to decodetree. These insns work by widening one or both inputs to double their size, performing an add or subtract at the doubled size and then storing the double-size result. As usual, rather than copying the loop of the original decoder (which needs awkward code to avoid problems when source and destination registers overlap) we just unroll the two passes. Backports commit b28be09570d0827969b62b8f82b0f720a9915427 from qemu		2020-06-16 23:29:53 -04:00
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arm	target/arm: Convert Neon 3-reg-diff prewidening ops to decodetree	2020-06-16 23:29:53 -04:00
i386	target/i386: Remove obsolete TODO file	2020-06-15 13:22:56 -04:00
m68k	target/m68k: implement opcode fetoxm1	2020-06-14 21:13:29 -04:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Add the lowRISC Ibex CPU	2020-06-14 22:28:55 -04:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00