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d30f99ca79
Convert the Neon logic ops in the 3-reg-same grouping to decodetree. Note that for the logic ops the 'size' field forms part of their decode and the actual operations are always bitwise. Backports commit 35a548edb6f5043386183b9f6b4139d99d1f130a from qemu
59 lines
2.5 KiB
Plaintext
59 lines
2.5 KiB
Plaintext
# AArch32 Neon data-processing instruction descriptions
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#
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# Copyright (c) 2020 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# VFP/Neon register fields; same as vfp.decode
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%vm_dp 5:1 0:4
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%vn_dp 7:1 16:4
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%vd_dp 22:1 12:4
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# Encodings for Neon data processing instructions where the T32 encoding
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# is a simple transformation of the A32 encoding.
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# More specifically, this file covers instructions where the A32 encoding is
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# 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
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# and the T32 encoding is
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# 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq
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# This file works on the A32 encoding only; calling code for T32 has to
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# transform the insn into the A32 version first.
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######################################################################
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# 3-reg-same grouping:
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# 1111 001 U 0 D sz:2 Vn:4 Vd:4 opc:4 N Q M op Vm:4
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######################################################################
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&3same vm vn vd q size
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@3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
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@3same_logic .... ... . . . .. .... .... .... . q:1 .. .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=0
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VAND_3s 1111 001 0 0 . 00 .... .... 0001 ... 1 .... @3same_logic
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VBIC_3s 1111 001 0 0 . 01 .... .... 0001 ... 1 .... @3same_logic
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VORR_3s 1111 001 0 0 . 10 .... .... 0001 ... 1 .... @3same_logic
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VORN_3s 1111 001 0 0 . 11 .... .... 0001 ... 1 .... @3same_logic
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VEOR_3s 1111 001 1 0 . 00 .... .... 0001 ... 1 .... @3same_logic
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VBSL_3s 1111 001 1 0 . 01 .... .... 0001 ... 1 .... @3same_logic
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VBIT_3s 1111 001 1 0 . 10 .... .... 0001 ... 1 .... @3same_logic
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VBIF_3s 1111 001 1 0 . 11 .... .... 0001 ... 1 .... @3same_logic
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VADD_3s 1111 001 0 0 . .. .... .... 1000 . . . 0 .... @3same
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VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0 .... @3same
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