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Aleksandar Markovic d70a2c1df1
target/mips: Update some CP0 registers bit definitions 
Update CP0 registers Config0, Config1, Config2, Config3,
Config4, and Config5 bit definitions.

Some of these bits will be utilized by upcoming nanoMIPS changes.

Backports commit 0413d7a55a8161ebd33541ba1df4285bf180c583 from qemu
2018-08-17 14:21:18 -04:00
..
arm target/arm: Fix aa64 FCADD and FCMLA decode 2018-08-17 14:06:01 -04:00
i386 i386: implement MSR_SMI_COUNT for TCG 2018-08-02 21:27:08 -04:00
m68k target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn 2018-06-15 11:40:18 -04:00
mips target/mips: Update some CP0 registers bit definitions 2018-08-17 14:21:18 -04:00
sparc tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-07 11:56:32 -04:00