Richard Henderson d81feac642 target/arm: Improve masking of SCR RES0 bits ... Protect reads of aa64 id registers with ARM_CP_STATE_AA64. Use this as a simpler test than arm_el_is_aa64, since EL3 cannot change mode. Backports commit 252e8c69669599b4bcff802df300726300292f47 from qemu		2021-02-25 13:56:35 -05:00
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arm	target/arm: Improve masking of SCR RES0 bits	2021-02-25 13:56:35 -05:00
i386	target/i386: reimplement fpatan using floatx80 operations	2021-02-25 13:48:32 -05:00
m68k	softfloat: merge floatx80_mod and floatx80_rem	2021-02-25 13:34:05 -05:00
mips	target/mips: Support variable page size	2020-06-14 21:09:51 -04:00
riscv	target/riscv: Implement checks for hfence	2021-02-25 12:03:57 -05:00
sparc	softfloat: Name compare relation enum	2020-05-21 18:08:52 -04:00