Peter Maydell d8eb259032 arm: Enforce should-be-1 bits in MRS decoding ... The MRS instruction requires that bits [19..16] are all 1s, and for A/R profile also that bits [7..0] are all 0s. At this point in the decode tree we have checked all of the rest of the instruction but were allowing these to be any value. If these bits are not set then the result is architecturally UNPREDICTABLE, but choosing to UNDEF is more helpful to the user and avoids unexpected odd behaviour if the encodings are used for some purpose in future architecture versions. Backports commit 3d54026fb06d1aea7ebb4e9825970b06bebcacac from qemu		2018-03-02 13:09:17 -05:00
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arm	arm: Enforce should-be-1 bits in MRS decoding	2018-03-02 13:09:17 -05:00
i386	i386: Change stepping of Haswell to non-blacklisted value	2018-03-02 12:53:11 -05:00
m68k	Move target-* CPU file into a target/ folder	2018-03-01 22:50:58 -05:00
mips	target-mips: Provide function to test if a CPU supports an ISA	2018-03-02 08:20:19 -05:00
sparc	cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap	2018-03-02 10:12:40 -05:00