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c7f6786089
There is no "version 2" of the "Lesser" General Public License. It is either "GPL version 2.0" or "Lesser GPL version 2.1". This patch replaces all occurrences of "Lesser GPL version 2" with "Lesser GPL version 2.1" in comment section. Backports 50f57e09fda4b7ffbc5ba62aad6cebf660824023
246 lines
11 KiB
Plaintext
246 lines
11 KiB
Plaintext
# AArch32 VFP instruction descriptions (conditional insns)
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#
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# Copyright (c) 2019 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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# Encodings for the conditional VFP instructions are here:
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# generally anything matching A32
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# cccc 11.. .... .... .... 101. .... ....
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# and T32
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# 1110 110. .... .... .... 101. .... ....
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# 1110 1110 .... .... .... 101. .... ....
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# (but those patterns might also cover some Neon instructions,
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# which do not live in this file.)
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# VFP registers have an odd encoding with a four-bit field
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# and a one-bit field which are assembled in different orders
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# depending on whether the register is double or single precision.
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# Each individual instruction function must do the checks for
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# "double register selected but CPU does not have double support"
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# and "double register number has bit 4 set but CPU does not
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# support D16-D31" (which should UNDEF).
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%vm_dp 5:1 0:4
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%vm_sp 0:4 5:1
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%vn_dp 7:1 16:4
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%vn_sp 16:4 7:1
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%vd_dp 22:1 12:4
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%vd_sp 12:4 22:1
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%vmov_idx_b 21:1 5:2
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%vmov_idx_h 21:1 6:1
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%vmov_imm 16:4 0:4
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@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp
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@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp
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@vfp_dm_ss ................................ vm=%vm_sp vd=%vd_sp
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@vfp_dm_dd ................................ vm=%vm_dp vd=%vd_dp
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@vfp_dm_ds ................................ vm=%vm_sp vd=%vd_dp
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@vfp_dm_sd ................................ vm=%vm_dp vd=%vd_sp
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# VMOV scalar to general-purpose register; note that this does
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# include some Neon cases.
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VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \
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vn=%vn_dp size=0 index=%vmov_idx_b
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VMOV_to_gp ---- 1110 u:1 0. 1 .... rt:4 1011 ..1 1 0000 \
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vn=%vn_dp size=1 index=%vmov_idx_h
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VMOV_to_gp ---- 1110 0 0 index:1 1 .... rt:4 1011 .00 1 0000 \
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vn=%vn_dp size=2 u=0
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VMOV_from_gp ---- 1110 0 1. 0 .... rt:4 1011 ... 1 0000 \
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vn=%vn_dp size=0 index=%vmov_idx_b
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VMOV_from_gp ---- 1110 0 0. 0 .... rt:4 1011 ..1 1 0000 \
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vn=%vn_dp size=1 index=%vmov_idx_h
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VMOV_from_gp ---- 1110 0 0 index:1 0 .... rt:4 1011 .00 1 0000 \
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vn=%vn_dp size=2
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VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e:1 1 0000 \
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vn=%vn_dp
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VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
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VMOV_half ---- 1110 000 l:1 .... rt:4 1001 . 001 0000 vn=%vn_sp
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VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=%vn_sp
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VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
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VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp
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VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp
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VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
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VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
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# We split the load/store multiple up into two patterns to avoid
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# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
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# grouping:
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# P=0 U=0 W=0 is 64-bit VMOV
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# P=1 W=0 is VLDR/VSTR
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# P=U W=1 is UNDEF
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# leaving P=0 U=1 W=x and P=1 U=0 W=1 for load/store multiple.
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# These include FSTM/FLDM.
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VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \
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vd=%vd_sp p=0 u=1
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VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \
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vd=%vd_dp p=0 u=1
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VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \
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vd=%vd_sp p=1 u=0 w=1
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VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
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vd=%vd_dp p=1 u=0 w=1
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# 3-register VFP data-processing; bits [23,21:20,6] identify the operation.
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VMLA_hp ---- 1110 0.00 .... .... 1001 .0.0 .... @vfp_dnm_s
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VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s
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VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d
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VMLS_hp ---- 1110 0.00 .... .... 1001 .1.0 .... @vfp_dnm_s
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VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s
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VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d
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VNMLS_hp ---- 1110 0.01 .... .... 1001 .0.0 .... @vfp_dnm_s
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VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s
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VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d
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VNMLA_hp ---- 1110 0.01 .... .... 1001 .1.0 .... @vfp_dnm_s
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VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s
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VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d
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VMUL_hp ---- 1110 0.10 .... .... 1001 .0.0 .... @vfp_dnm_s
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VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s
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VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d
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VNMUL_hp ---- 1110 0.10 .... .... 1001 .1.0 .... @vfp_dnm_s
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VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s
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VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d
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VADD_hp ---- 1110 0.11 .... .... 1001 .0.0 .... @vfp_dnm_s
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VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s
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VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d
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VSUB_hp ---- 1110 0.11 .... .... 1001 .1.0 .... @vfp_dnm_s
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VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s
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VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d
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VDIV_hp ---- 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s
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VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s
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VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d
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VFMA_hp ---- 1110 1.10 .... .... 1001 .0. 0 .... @vfp_dnm_s
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VFMS_hp ---- 1110 1.10 .... .... 1001 .1. 0 .... @vfp_dnm_s
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VFNMA_hp ---- 1110 1.01 .... .... 1001 .0. 0 .... @vfp_dnm_s
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VFNMS_hp ---- 1110 1.01 .... .... 1001 .1. 0 .... @vfp_dnm_s
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VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s
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VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s
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VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s
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VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s
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VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d
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VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d
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VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d
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VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d
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VMOV_imm_hp ---- 1110 1.11 .... .... 1001 0000 .... \
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vd=%vd_sp imm=%vmov_imm
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VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \
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vd=%vd_sp imm=%vmov_imm
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VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \
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vd=%vd_dp imm=%vmov_imm
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VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss
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VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd
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VABS_hp ---- 1110 1.11 0000 .... 1001 11.0 .... @vfp_dm_ss
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VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss
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VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd
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VNEG_hp ---- 1110 1.11 0001 .... 1001 01.0 .... @vfp_dm_ss
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VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss
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VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd
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VSQRT_hp ---- 1110 1.11 0001 .... 1001 11.0 .... @vfp_dm_ss
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VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss
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VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd
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VCMP_hp ---- 1110 1.11 010 z:1 .... 1001 e:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCMP_dp ---- 1110 1.11 010 z:1 .... 1011 e:1 1.0 .... \
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vd=%vd_dp vm=%vm_dp
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# VCVTT and VCVTB from f16: Vd format depends on size bit; Vm is always vm_sp
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VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \
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vd=%vd_dp vm=%vm_sp
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# VCVTB and VCVTT to f16: Vd format is always vd_sp;
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# Vm format depends on size bit
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VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \
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vd=%vd_sp vm=%vm_dp
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VRINTR_hp ---- 1110 1.11 0110 .... 1001 01.0 .... @vfp_dm_ss
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VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss
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VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd
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VRINTZ_hp ---- 1110 1.11 0110 .... 1001 11.0 .... @vfp_dm_ss
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VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss
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VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd
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VRINTX_hp ---- 1110 1.11 0111 .... 1001 01.0 .... @vfp_dm_ss
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VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss
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VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd
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# VCVT between single and double:
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# Vm precision depends on size; Vd is its reverse
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VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds
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VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd
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# VCVT from integer to floating point: Vm always single; Vd depends on size
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VCVT_int_hp ---- 1110 1.11 1000 .... 1001 s:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 .... \
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vd=%vd_dp vm=%vm_sp
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# VJCVT is always dp to sp
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VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd
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# VCVT between floating-point and fixed-point. The immediate value
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# is in the same format as a Vm single-precision register number.
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# We assemble bits 18 (op), 16 (u) and 7 (sx) into a single opc field
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# for the convenience of the trans_VCVT_fix functions.
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%vcvt_fix_op 18:1 16:1 7:1
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VCVT_fix_hp ---- 1110 1.11 1.1. .... 1001 .1.0 .... \
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vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
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VCVT_fix_sp ---- 1110 1.11 1.1. .... 1010 .1.0 .... \
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vd=%vd_sp imm=%vm_sp opc=%vcvt_fix_op
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VCVT_fix_dp ---- 1110 1.11 1.1. .... 1011 .1.0 .... \
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vd=%vd_dp imm=%vm_sp opc=%vcvt_fix_op
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# VCVT float to integer (VCVT and VCVTR): Vd always single; Vd depends on size
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VCVT_hp_int ---- 1110 1.11 110 s:1 .... 1001 rz:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 .... \
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vd=%vd_sp vm=%vm_sp
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VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \
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vd=%vd_sp vm=%vm_dp
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